crypto/ccree/cc_hash.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
0003
0004 /* \file cc_hash.h
0005  * ARM CryptoCell Hash Crypto API
0006  */
0007
0008 #ifndef __CC_HASH_H__
0009 #define __CC_HASH_H__
0010
0011 #include "cc_buffer_mgr.h"
0012
0013 #define HMAC_IPAD_CONST 0x36363636
0014 #define HMAC_OPAD_CONST 0x5C5C5C5C
0015 #define HASH_LEN_SIZE_712 16
0016 #define HASH_LEN_SIZE_630 8
0017 #define HASH_MAX_LEN_SIZE HASH_LEN_SIZE_712
0018 #define CC_MAX_HASH_DIGEST_SIZE SHA512_DIGEST_SIZE
0019 #define CC_MAX_HASH_BLCK_SIZE SHA512_BLOCK_SIZE
0020
0021 #define XCBC_MAC_K1_OFFSET 0
0022 #define XCBC_MAC_K2_OFFSET 16
0023 #define XCBC_MAC_K3_OFFSET 32
0024
0025 #define CC_EXPORT_MAGIC 0xC2EE1070U
0026
0027 /* this struct was taken from drivers/crypto/nx/nx-aes-xcbc.c and it is used
0028  * for xcbc/cmac statesize
0029  */
0030 struct aeshash_state {
0031     u8 state[AES_BLOCK_SIZE];
0032     unsigned int count;
0033     u8 buffer[AES_BLOCK_SIZE];
0034 };
0035
0036 /* ahash state */
0037 struct ahash_req_ctx {
0038     u8 buffers[2][CC_MAX_HASH_BLCK_SIZE] ____cacheline_aligned;
0039     u8 digest_result_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
0040     u8 digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
0041     u8 opad_digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
0042     u8 digest_bytes_len[HASH_MAX_LEN_SIZE] ____cacheline_aligned;
0043     struct async_gen_req_ctx gen_ctx ____cacheline_aligned;
0044     enum cc_req_dma_buf_type data_dma_buf_type;
0045     dma_addr_t opad_digest_dma_addr;
0046     dma_addr_t digest_buff_dma_addr;
0047     dma_addr_t digest_bytes_len_dma_addr;
0048     dma_addr_t digest_result_dma_addr;
0049     u32 buf_cnt[2];
0050     u32 buff_index;
0051     u32 xcbc_count; /* count xcbc update operatations */
0052     struct scatterlist buff_sg[2];
0053     struct scatterlist *curr_sg;
0054     u32 in_nents;
0055     u32 mlli_nents;
0056     struct mlli_params mlli_params;
0057 };
0058
0059 static inline u32 *cc_hash_buf_cnt(struct ahash_req_ctx *state)
0060 {
0061     return &state->buf_cnt[state->buff_index];
0062 }
0063
0064 static inline u8 *cc_hash_buf(struct ahash_req_ctx *state)
0065 {
0066     return state->buffers[state->buff_index];
0067 }
0068
0069 static inline u32 *cc_next_buf_cnt(struct ahash_req_ctx *state)
0070 {
0071     return &state->buf_cnt[state->buff_index ^ 1];
0072 }
0073
0074 static inline u8 *cc_next_buf(struct ahash_req_ctx *state)
0075 {
0076     return state->buffers[state->buff_index ^ 1];
0077 }
0078
0079 int cc_hash_alloc(struct cc_drvdata *drvdata);
0080 int cc_init_hash_sram(struct cc_drvdata *drvdata);
0081 int cc_hash_free(struct cc_drvdata *drvdata);
0082
0083 /**
0084  * cc_digest_len_addr() - Gets the initial digest length
0085  *
0086  * @drvdata: Associated device driver context
0087  * @mode: The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512
0088  *
0089  * Return:
0090  * Returns the address of the initial digest length in SRAM
0091  */
0092 u32 cc_digest_len_addr(void *drvdata, u32 mode);
0093
0094 /**
0095  * cc_larval_digest_addr() - Gets the address of the initial digest in SRAM
0096  * according to the given hash mode
0097  *
0098  * @drvdata: Associated device driver context
0099  * @mode: The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512
0100  *
0101  * Return:
0102  * The address of the initial digest in SRAM
0103  */
0104 u32 cc_larval_digest_addr(void *drvdata, u32 mode);
0105
0106 #endif /*__CC_HASH_H__*/