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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright (C) 2012-2019 ARM Limited or its affiliates. */
0003 
0004 #include <linux/kernel.h>
0005 #include <linux/module.h>
0006 
0007 #include <linux/crypto.h>
0008 #include <linux/moduleparam.h>
0009 #include <linux/types.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/slab.h>
0013 #include <linux/spinlock.h>
0014 #include <linux/of.h>
0015 #include <linux/clk.h>
0016 #include <linux/of_address.h>
0017 #include <linux/of_device.h>
0018 #include <linux/pm_runtime.h>
0019 
0020 #include "cc_driver.h"
0021 #include "cc_request_mgr.h"
0022 #include "cc_buffer_mgr.h"
0023 #include "cc_debugfs.h"
0024 #include "cc_cipher.h"
0025 #include "cc_aead.h"
0026 #include "cc_hash.h"
0027 #include "cc_sram_mgr.h"
0028 #include "cc_pm.h"
0029 #include "cc_fips.h"
0030 
0031 bool cc_dump_desc;
0032 module_param_named(dump_desc, cc_dump_desc, bool, 0600);
0033 MODULE_PARM_DESC(cc_dump_desc, "Dump descriptors to kernel log as debugging aid");
0034 bool cc_dump_bytes;
0035 module_param_named(dump_bytes, cc_dump_bytes, bool, 0600);
0036 MODULE_PARM_DESC(cc_dump_bytes, "Dump buffers to kernel log as debugging aid");
0037 
0038 static bool cc_sec_disable;
0039 module_param_named(sec_disable, cc_sec_disable, bool, 0600);
0040 MODULE_PARM_DESC(cc_sec_disable, "Disable security functions");
0041 
0042 struct cc_hw_data {
0043     char *name;
0044     enum cc_hw_rev rev;
0045     u32 sig;
0046     u32 cidr_0123;
0047     u32 pidr_0124;
0048     int std_bodies;
0049 };
0050 
0051 #define CC_NUM_IDRS 4
0052 #define CC_HW_RESET_LOOP_COUNT 10
0053 
0054 /* Note: PIDR3 holds CMOD/Rev so ignored for HW identification purposes */
0055 static const u32 pidr_0124_offsets[CC_NUM_IDRS] = {
0056     CC_REG(PERIPHERAL_ID_0), CC_REG(PERIPHERAL_ID_1),
0057     CC_REG(PERIPHERAL_ID_2), CC_REG(PERIPHERAL_ID_4)
0058 };
0059 
0060 static const u32 cidr_0123_offsets[CC_NUM_IDRS] = {
0061     CC_REG(COMPONENT_ID_0), CC_REG(COMPONENT_ID_1),
0062     CC_REG(COMPONENT_ID_2), CC_REG(COMPONENT_ID_3)
0063 };
0064 
0065 /* Hardware revisions defs. */
0066 
0067 /* The 703 is a OSCCA only variant of the 713 */
0068 static const struct cc_hw_data cc703_hw = {
0069     .name = "703", .rev = CC_HW_REV_713, .cidr_0123 = 0xB105F00DU,
0070     .pidr_0124 = 0x040BB0D0U, .std_bodies = CC_STD_OSCCA
0071 };
0072 
0073 static const struct cc_hw_data cc713_hw = {
0074     .name = "713", .rev = CC_HW_REV_713, .cidr_0123 = 0xB105F00DU,
0075     .pidr_0124 = 0x040BB0D0U, .std_bodies = CC_STD_ALL
0076 };
0077 
0078 static const struct cc_hw_data cc712_hw = {
0079     .name = "712", .rev = CC_HW_REV_712, .sig =  0xDCC71200U,
0080     .std_bodies = CC_STD_ALL
0081 };
0082 
0083 static const struct cc_hw_data cc710_hw = {
0084     .name = "710", .rev = CC_HW_REV_710, .sig =  0xDCC63200U,
0085     .std_bodies = CC_STD_ALL
0086 };
0087 
0088 static const struct cc_hw_data cc630p_hw = {
0089     .name = "630P", .rev = CC_HW_REV_630, .sig = 0xDCC63000U,
0090     .std_bodies = CC_STD_ALL
0091 };
0092 
0093 static const struct of_device_id arm_ccree_dev_of_match[] = {
0094     { .compatible = "arm,cryptocell-703-ree", .data = &cc703_hw },
0095     { .compatible = "arm,cryptocell-713-ree", .data = &cc713_hw },
0096     { .compatible = "arm,cryptocell-712-ree", .data = &cc712_hw },
0097     { .compatible = "arm,cryptocell-710-ree", .data = &cc710_hw },
0098     { .compatible = "arm,cryptocell-630p-ree", .data = &cc630p_hw },
0099     {}
0100 };
0101 MODULE_DEVICE_TABLE(of, arm_ccree_dev_of_match);
0102 
0103 static void init_cc_cache_params(struct cc_drvdata *drvdata)
0104 {
0105     struct device *dev = drvdata_to_dev(drvdata);
0106     u32 cache_params, ace_const, val;
0107     u64 mask;
0108 
0109     /* compute CC_AXIM_CACHE_PARAMS */
0110     cache_params = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS));
0111     dev_dbg(dev, "Cache params previous: 0x%08X\n", cache_params);
0112 
0113     /* non cached or write-back, write allocate */
0114     val = drvdata->coherent ? 0xb : 0x2;
0115 
0116     mask = CC_GENMASK(CC_AXIM_CACHE_PARAMS_AWCACHE);
0117     cache_params &= ~mask;
0118     cache_params |= FIELD_PREP(mask, val);
0119 
0120     mask = CC_GENMASK(CC_AXIM_CACHE_PARAMS_AWCACHE_LAST);
0121     cache_params &= ~mask;
0122     cache_params |= FIELD_PREP(mask, val);
0123 
0124     mask = CC_GENMASK(CC_AXIM_CACHE_PARAMS_ARCACHE);
0125     cache_params &= ~mask;
0126     cache_params |= FIELD_PREP(mask, val);
0127 
0128     drvdata->cache_params = cache_params;
0129 
0130     dev_dbg(dev, "Cache params current: 0x%08X\n", cache_params);
0131 
0132     if (drvdata->hw_rev <= CC_HW_REV_710)
0133         return;
0134 
0135     /* compute CC_AXIM_ACE_CONST */
0136     ace_const = cc_ioread(drvdata, CC_REG(AXIM_ACE_CONST));
0137     dev_dbg(dev, "ACE-const previous: 0x%08X\n", ace_const);
0138 
0139     /* system or outer-sharable */
0140     val = drvdata->coherent ? 0x2 : 0x3;
0141 
0142     mask = CC_GENMASK(CC_AXIM_ACE_CONST_ARDOMAIN);
0143     ace_const &= ~mask;
0144     ace_const |= FIELD_PREP(mask, val);
0145 
0146     mask = CC_GENMASK(CC_AXIM_ACE_CONST_AWDOMAIN);
0147     ace_const &= ~mask;
0148     ace_const |= FIELD_PREP(mask, val);
0149 
0150     dev_dbg(dev, "ACE-const current: 0x%08X\n", ace_const);
0151 
0152     drvdata->ace_const = ace_const;
0153 }
0154 
0155 static u32 cc_read_idr(struct cc_drvdata *drvdata, const u32 *idr_offsets)
0156 {
0157     int i;
0158     union {
0159         u8 regs[CC_NUM_IDRS];
0160         __le32 val;
0161     } idr;
0162 
0163     for (i = 0; i < CC_NUM_IDRS; ++i)
0164         idr.regs[i] = cc_ioread(drvdata, idr_offsets[i]);
0165 
0166     return le32_to_cpu(idr.val);
0167 }
0168 
0169 void __dump_byte_array(const char *name, const u8 *buf, size_t len)
0170 {
0171     char prefix[64];
0172 
0173     if (!buf)
0174         return;
0175 
0176     snprintf(prefix, sizeof(prefix), "%s[%zu]: ", name, len);
0177 
0178     print_hex_dump(KERN_DEBUG, prefix, DUMP_PREFIX_ADDRESS, 16, 1, buf,
0179                len, false);
0180 }
0181 
0182 static irqreturn_t cc_isr(int irq, void *dev_id)
0183 {
0184     struct cc_drvdata *drvdata = (struct cc_drvdata *)dev_id;
0185     struct device *dev = drvdata_to_dev(drvdata);
0186     u32 irr;
0187     u32 imr;
0188 
0189     /* STAT_OP_TYPE_GENERIC STAT_PHASE_0: Interrupt */
0190     /* if driver suspended return, probably shared interrupt */
0191     if (pm_runtime_suspended(dev))
0192         return IRQ_NONE;
0193 
0194     /* read the interrupt status */
0195     irr = cc_ioread(drvdata, CC_REG(HOST_IRR));
0196     dev_dbg(dev, "Got IRR=0x%08X\n", irr);
0197 
0198     if (irr == 0) /* Probably shared interrupt line */
0199         return IRQ_NONE;
0200 
0201     imr = cc_ioread(drvdata, CC_REG(HOST_IMR));
0202 
0203     /* clear interrupt - must be before processing events */
0204     cc_iowrite(drvdata, CC_REG(HOST_ICR), irr);
0205 
0206     drvdata->irq = irr;
0207     /* Completion interrupt - most probable */
0208     if (irr & drvdata->comp_mask) {
0209         /* Mask all completion interrupts - will be unmasked in
0210          * deferred service handler
0211          */
0212         cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | drvdata->comp_mask);
0213         irr &= ~drvdata->comp_mask;
0214         complete_request(drvdata);
0215     }
0216 #ifdef CONFIG_CRYPTO_FIPS
0217     /* TEE FIPS interrupt */
0218     if (irr & CC_GPR0_IRQ_MASK) {
0219         /* Mask interrupt - will be unmasked in Deferred service
0220          * handler
0221          */
0222         cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | CC_GPR0_IRQ_MASK);
0223         irr &= ~CC_GPR0_IRQ_MASK;
0224         fips_handler(drvdata);
0225     }
0226 #endif
0227     /* AXI error interrupt */
0228     if (irr & CC_AXI_ERR_IRQ_MASK) {
0229         u32 axi_err;
0230 
0231         /* Read the AXI error ID */
0232         axi_err = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR));
0233         dev_dbg(dev, "AXI completion error: axim_mon_err=0x%08X\n",
0234             axi_err);
0235 
0236         irr &= ~CC_AXI_ERR_IRQ_MASK;
0237     }
0238 
0239     if (irr) {
0240         dev_dbg_ratelimited(dev, "IRR includes unknown cause bits (0x%08X)\n",
0241                     irr);
0242         /* Just warning */
0243     }
0244 
0245     return IRQ_HANDLED;
0246 }
0247 
0248 bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata)
0249 {
0250     unsigned int val;
0251     unsigned int i;
0252 
0253     /* 712/710/63 has no reset completion indication, always return true */
0254     if (drvdata->hw_rev <= CC_HW_REV_712)
0255         return true;
0256 
0257     for (i = 0; i < CC_HW_RESET_LOOP_COUNT; i++) {
0258         /* in cc7x3 NVM_IS_IDLE indicates that CC reset is
0259          *  completed and device is fully functional
0260          */
0261         val = cc_ioread(drvdata, CC_REG(NVM_IS_IDLE));
0262         if (val & CC_NVM_IS_IDLE_MASK) {
0263             /* hw indicate reset completed */
0264             return true;
0265         }
0266         /* allow scheduling other process on the processor */
0267         schedule();
0268     }
0269     /* reset not completed */
0270     return false;
0271 }
0272 
0273 int init_cc_regs(struct cc_drvdata *drvdata)
0274 {
0275     unsigned int val;
0276     struct device *dev = drvdata_to_dev(drvdata);
0277 
0278     /* Unmask all AXI interrupt sources AXI_CFG1 register   */
0279     /* AXI interrupt config are obsoleted startign at cc7x3 */
0280     if (drvdata->hw_rev <= CC_HW_REV_712) {
0281         val = cc_ioread(drvdata, CC_REG(AXIM_CFG));
0282         cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~CC_AXI_IRQ_MASK);
0283         dev_dbg(dev, "AXIM_CFG=0x%08X\n",
0284             cc_ioread(drvdata, CC_REG(AXIM_CFG)));
0285     }
0286 
0287     /* Clear all pending interrupts */
0288     val = cc_ioread(drvdata, CC_REG(HOST_IRR));
0289     dev_dbg(dev, "IRR=0x%08X\n", val);
0290     cc_iowrite(drvdata, CC_REG(HOST_ICR), val);
0291 
0292     /* Unmask relevant interrupt cause */
0293     val = drvdata->comp_mask | CC_AXI_ERR_IRQ_MASK;
0294 
0295     if (drvdata->hw_rev >= CC_HW_REV_712)
0296         val |= CC_GPR0_IRQ_MASK;
0297 
0298     cc_iowrite(drvdata, CC_REG(HOST_IMR), ~val);
0299 
0300     cc_iowrite(drvdata, CC_REG(AXIM_CACHE_PARAMS), drvdata->cache_params);
0301     if (drvdata->hw_rev >= CC_HW_REV_712)
0302         cc_iowrite(drvdata, CC_REG(AXIM_ACE_CONST), drvdata->ace_const);
0303 
0304     return 0;
0305 }
0306 
0307 static int init_cc_resources(struct platform_device *plat_dev)
0308 {
0309     struct resource *req_mem_cc_regs = NULL;
0310     struct cc_drvdata *new_drvdata;
0311     struct device *dev = &plat_dev->dev;
0312     struct device_node *np = dev->of_node;
0313     u32 val, hw_rev_pidr, sig_cidr;
0314     u64 dma_mask;
0315     const struct cc_hw_data *hw_rev;
0316     struct clk *clk;
0317     int irq;
0318     int rc = 0;
0319 
0320     new_drvdata = devm_kzalloc(dev, sizeof(*new_drvdata), GFP_KERNEL);
0321     if (!new_drvdata)
0322         return -ENOMEM;
0323 
0324     hw_rev = of_device_get_match_data(dev);
0325     new_drvdata->hw_rev_name = hw_rev->name;
0326     new_drvdata->hw_rev = hw_rev->rev;
0327     new_drvdata->std_bodies = hw_rev->std_bodies;
0328 
0329     if (hw_rev->rev >= CC_HW_REV_712) {
0330         new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP);
0331         new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_712);
0332         new_drvdata->ver_offset = CC_REG(HOST_VERSION_712);
0333     } else {
0334         new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8);
0335         new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_630);
0336         new_drvdata->ver_offset = CC_REG(HOST_VERSION_630);
0337     }
0338 
0339     new_drvdata->comp_mask = CC_COMP_IRQ_MASK;
0340 
0341     platform_set_drvdata(plat_dev, new_drvdata);
0342     new_drvdata->plat_dev = plat_dev;
0343 
0344     clk = devm_clk_get_optional(dev, NULL);
0345     if (IS_ERR(clk))
0346         return dev_err_probe(dev, PTR_ERR(clk), "Error getting clock\n");
0347     new_drvdata->clk = clk;
0348 
0349     new_drvdata->coherent = of_dma_is_coherent(np);
0350 
0351     /* Get device resources */
0352     /* First CC registers space */
0353     req_mem_cc_regs = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
0354     /* Map registers space */
0355     new_drvdata->cc_base = devm_ioremap_resource(dev, req_mem_cc_regs);
0356     if (IS_ERR(new_drvdata->cc_base))
0357         return PTR_ERR(new_drvdata->cc_base);
0358 
0359     dev_dbg(dev, "Got MEM resource (%s): %pR\n", req_mem_cc_regs->name,
0360         req_mem_cc_regs);
0361     dev_dbg(dev, "CC registers mapped from %pa to 0x%p\n",
0362         &req_mem_cc_regs->start, new_drvdata->cc_base);
0363 
0364     /* Then IRQ */
0365     irq = platform_get_irq(plat_dev, 0);
0366     if (irq < 0)
0367         return irq;
0368 
0369     init_completion(&new_drvdata->hw_queue_avail);
0370 
0371     if (!dev->dma_mask)
0372         dev->dma_mask = &dev->coherent_dma_mask;
0373 
0374     dma_mask = DMA_BIT_MASK(DMA_BIT_MASK_LEN);
0375     rc = dma_set_coherent_mask(dev, dma_mask);
0376     if (rc) {
0377         dev_err(dev, "Failed in dma_set_coherent_mask, mask=%llx\n",
0378             dma_mask);
0379         return rc;
0380     }
0381 
0382     rc = clk_prepare_enable(new_drvdata->clk);
0383     if (rc) {
0384         dev_err(dev, "Failed to enable clock");
0385         return rc;
0386     }
0387 
0388     new_drvdata->sec_disabled = cc_sec_disable;
0389 
0390     pm_runtime_set_autosuspend_delay(dev, CC_SUSPEND_TIMEOUT);
0391     pm_runtime_use_autosuspend(dev);
0392     pm_runtime_set_active(dev);
0393     pm_runtime_enable(dev);
0394     rc = pm_runtime_get_sync(dev);
0395     if (rc < 0) {
0396         dev_err(dev, "pm_runtime_get_sync() failed: %d\n", rc);
0397         goto post_pm_err;
0398     }
0399 
0400     /* Wait for Cryptocell reset completion */
0401     if (!cc_wait_for_reset_completion(new_drvdata)) {
0402         dev_err(dev, "Cryptocell reset not completed");
0403     }
0404 
0405     if (hw_rev->rev <= CC_HW_REV_712) {
0406         /* Verify correct mapping */
0407         val = cc_ioread(new_drvdata, new_drvdata->sig_offset);
0408         if (val != hw_rev->sig) {
0409             dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n",
0410                 val, hw_rev->sig);
0411             rc = -EINVAL;
0412             goto post_pm_err;
0413         }
0414         sig_cidr = val;
0415         hw_rev_pidr = cc_ioread(new_drvdata, new_drvdata->ver_offset);
0416     } else {
0417         /* Verify correct mapping */
0418         val = cc_read_idr(new_drvdata, pidr_0124_offsets);
0419         if (val != hw_rev->pidr_0124) {
0420             dev_err(dev, "Invalid CC PIDR: PIDR0124=0x%08X != expected=0x%08X\n",
0421                 val,  hw_rev->pidr_0124);
0422             rc = -EINVAL;
0423             goto post_pm_err;
0424         }
0425         hw_rev_pidr = val;
0426 
0427         val = cc_read_idr(new_drvdata, cidr_0123_offsets);
0428         if (val != hw_rev->cidr_0123) {
0429             dev_err(dev, "Invalid CC CIDR: CIDR0123=0x%08X != expected=0x%08X\n",
0430             val,  hw_rev->cidr_0123);
0431             rc = -EINVAL;
0432             goto post_pm_err;
0433         }
0434         sig_cidr = val;
0435 
0436         /* Check HW engine configuration */
0437         val = cc_ioread(new_drvdata, CC_REG(HOST_REMOVE_INPUT_PINS));
0438         switch (val) {
0439         case CC_PINS_FULL:
0440             /* This is fine */
0441             break;
0442         case CC_PINS_SLIM:
0443             if (new_drvdata->std_bodies & CC_STD_NIST) {
0444                 dev_warn(dev, "703 mode forced due to HW configuration.\n");
0445                 new_drvdata->std_bodies = CC_STD_OSCCA;
0446             }
0447             break;
0448         default:
0449             dev_err(dev, "Unsupported engines configuration.\n");
0450             rc = -EINVAL;
0451             goto post_pm_err;
0452         }
0453 
0454         /* Check security disable state */
0455         val = cc_ioread(new_drvdata, CC_REG(SECURITY_DISABLED));
0456         val &= CC_SECURITY_DISABLED_MASK;
0457         new_drvdata->sec_disabled |= !!val;
0458 
0459         if (!new_drvdata->sec_disabled) {
0460             new_drvdata->comp_mask |= CC_CPP_SM4_ABORT_MASK;
0461             if (new_drvdata->std_bodies & CC_STD_NIST)
0462                 new_drvdata->comp_mask |= CC_CPP_AES_ABORT_MASK;
0463         }
0464     }
0465 
0466     if (new_drvdata->sec_disabled)
0467         dev_info(dev, "Security Disabled mode is in effect. Security functions disabled.\n");
0468 
0469     /* Display HW versions */
0470     dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X/0x%8X, Driver version %s\n",
0471          hw_rev->name, hw_rev_pidr, sig_cidr, DRV_MODULE_VERSION);
0472     /* register the driver isr function */
0473     rc = devm_request_irq(dev, irq, cc_isr, IRQF_SHARED, "ccree",
0474                   new_drvdata);
0475     if (rc) {
0476         dev_err(dev, "Could not register to interrupt %d\n", irq);
0477         goto post_pm_err;
0478     }
0479     dev_dbg(dev, "Registered to IRQ: %d\n", irq);
0480 
0481     init_cc_cache_params(new_drvdata);
0482 
0483     rc = init_cc_regs(new_drvdata);
0484     if (rc) {
0485         dev_err(dev, "init_cc_regs failed\n");
0486         goto post_pm_err;
0487     }
0488 
0489     rc = cc_debugfs_init(new_drvdata);
0490     if (rc) {
0491         dev_err(dev, "Failed registering debugfs interface\n");
0492         goto post_regs_err;
0493     }
0494 
0495     rc = cc_fips_init(new_drvdata);
0496     if (rc) {
0497         dev_err(dev, "cc_fips_init failed 0x%x\n", rc);
0498         goto post_debugfs_err;
0499     }
0500     rc = cc_sram_mgr_init(new_drvdata);
0501     if (rc) {
0502         dev_err(dev, "cc_sram_mgr_init failed\n");
0503         goto post_fips_init_err;
0504     }
0505 
0506     new_drvdata->mlli_sram_addr =
0507         cc_sram_alloc(new_drvdata, MAX_MLLI_BUFF_SIZE);
0508     if (new_drvdata->mlli_sram_addr == NULL_SRAM_ADDR) {
0509         rc = -ENOMEM;
0510         goto post_fips_init_err;
0511     }
0512 
0513     rc = cc_req_mgr_init(new_drvdata);
0514     if (rc) {
0515         dev_err(dev, "cc_req_mgr_init failed\n");
0516         goto post_fips_init_err;
0517     }
0518 
0519     rc = cc_buffer_mgr_init(new_drvdata);
0520     if (rc) {
0521         dev_err(dev, "cc_buffer_mgr_init failed\n");
0522         goto post_req_mgr_err;
0523     }
0524 
0525     /* hash must be allocated first due to use of send_request_init()
0526      * and dependency of AEAD on it
0527      */
0528     rc = cc_hash_alloc(new_drvdata);
0529     if (rc) {
0530         dev_err(dev, "cc_hash_alloc failed\n");
0531         goto post_buf_mgr_err;
0532     }
0533 
0534     /* Allocate crypto algs */
0535     rc = cc_cipher_alloc(new_drvdata);
0536     if (rc) {
0537         dev_err(dev, "cc_cipher_alloc failed\n");
0538         goto post_hash_err;
0539     }
0540 
0541     rc = cc_aead_alloc(new_drvdata);
0542     if (rc) {
0543         dev_err(dev, "cc_aead_alloc failed\n");
0544         goto post_cipher_err;
0545     }
0546 
0547     /* If we got here and FIPS mode is enabled
0548      * it means all FIPS test passed, so let TEE
0549      * know we're good.
0550      */
0551     cc_set_ree_fips_status(new_drvdata, true);
0552 
0553     pm_runtime_put(dev);
0554     return 0;
0555 
0556 post_cipher_err:
0557     cc_cipher_free(new_drvdata);
0558 post_hash_err:
0559     cc_hash_free(new_drvdata);
0560 post_buf_mgr_err:
0561      cc_buffer_mgr_fini(new_drvdata);
0562 post_req_mgr_err:
0563     cc_req_mgr_fini(new_drvdata);
0564 post_fips_init_err:
0565     cc_fips_fini(new_drvdata);
0566 post_debugfs_err:
0567     cc_debugfs_fini(new_drvdata);
0568 post_regs_err:
0569     fini_cc_regs(new_drvdata);
0570 post_pm_err:
0571     pm_runtime_put_noidle(dev);
0572     pm_runtime_disable(dev);
0573     pm_runtime_set_suspended(dev);
0574     clk_disable_unprepare(new_drvdata->clk);
0575     return rc;
0576 }
0577 
0578 void fini_cc_regs(struct cc_drvdata *drvdata)
0579 {
0580     /* Mask all interrupts */
0581     cc_iowrite(drvdata, CC_REG(HOST_IMR), 0xFFFFFFFF);
0582 }
0583 
0584 static void cleanup_cc_resources(struct platform_device *plat_dev)
0585 {
0586     struct device *dev = &plat_dev->dev;
0587     struct cc_drvdata *drvdata =
0588         (struct cc_drvdata *)platform_get_drvdata(plat_dev);
0589 
0590     cc_aead_free(drvdata);
0591     cc_cipher_free(drvdata);
0592     cc_hash_free(drvdata);
0593     cc_buffer_mgr_fini(drvdata);
0594     cc_req_mgr_fini(drvdata);
0595     cc_fips_fini(drvdata);
0596     cc_debugfs_fini(drvdata);
0597     fini_cc_regs(drvdata);
0598     pm_runtime_put_noidle(dev);
0599     pm_runtime_disable(dev);
0600     pm_runtime_set_suspended(dev);
0601     clk_disable_unprepare(drvdata->clk);
0602 }
0603 
0604 unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata)
0605 {
0606     if (drvdata->hw_rev >= CC_HW_REV_712)
0607         return HASH_LEN_SIZE_712;
0608     else
0609         return HASH_LEN_SIZE_630;
0610 }
0611 
0612 static int ccree_probe(struct platform_device *plat_dev)
0613 {
0614     int rc;
0615     struct device *dev = &plat_dev->dev;
0616 
0617     /* Map registers space */
0618     rc = init_cc_resources(plat_dev);
0619     if (rc)
0620         return rc;
0621 
0622     dev_info(dev, "ARM ccree device initialized\n");
0623 
0624     return 0;
0625 }
0626 
0627 static int ccree_remove(struct platform_device *plat_dev)
0628 {
0629     struct device *dev = &plat_dev->dev;
0630 
0631     dev_dbg(dev, "Releasing ccree resources...\n");
0632 
0633     cleanup_cc_resources(plat_dev);
0634 
0635     dev_info(dev, "ARM ccree device terminated\n");
0636 
0637     return 0;
0638 }
0639 
0640 static struct platform_driver ccree_driver = {
0641     .driver = {
0642            .name = "ccree",
0643            .of_match_table = arm_ccree_dev_of_match,
0644 #ifdef CONFIG_PM
0645            .pm = &ccree_pm,
0646 #endif
0647     },
0648     .probe = ccree_probe,
0649     .remove = ccree_remove,
0650 };
0651 
0652 static int __init ccree_init(void)
0653 {
0654     cc_debugfs_global_init();
0655 
0656     return platform_driver_register(&ccree_driver);
0657 }
0658 module_init(ccree_init);
0659 
0660 static void __exit ccree_exit(void)
0661 {
0662     platform_driver_unregister(&ccree_driver);
0663     cc_debugfs_global_fini();
0664 }
0665 module_exit(ccree_exit);
0666 
0667 /* Module description */
0668 MODULE_DESCRIPTION("ARM TrustZone CryptoCell REE Driver");
0669 MODULE_VERSION(DRV_MODULE_VERSION);
0670 MODULE_AUTHOR("ARM");
0671 MODULE_LICENSE("GPL v2");
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