crypto/ccree/cc_crypto_ctx.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
0003
0004 #ifndef _CC_CRYPTO_CTX_H_
0005 #define _CC_CRYPTO_CTX_H_
0006
0007 #include <linux/types.h>
0008
0009 #define CC_DRV_DES_IV_SIZE 8
0010 #define CC_DRV_DES_BLOCK_SIZE 8
0011
0012 #define CC_DRV_DES_ONE_KEY_SIZE 8
0013 #define CC_DRV_DES_DOUBLE_KEY_SIZE 16
0014 #define CC_DRV_DES_TRIPLE_KEY_SIZE 24
0015 #define CC_DRV_DES_KEY_SIZE_MAX CC_DRV_DES_TRIPLE_KEY_SIZE
0016
0017 #define CC_AES_IV_SIZE 16
0018 #define CC_AES_IV_SIZE_WORDS (CC_AES_IV_SIZE >> 2)
0019
0020 #define CC_AES_BLOCK_SIZE 16
0021 #define CC_AES_BLOCK_SIZE_WORDS 4
0022
0023 #define CC_AES_128_BIT_KEY_SIZE 16
0024 #define CC_AES_128_BIT_KEY_SIZE_WORDS   (CC_AES_128_BIT_KEY_SIZE >> 2)
0025 #define CC_AES_192_BIT_KEY_SIZE 24
0026 #define CC_AES_192_BIT_KEY_SIZE_WORDS   (CC_AES_192_BIT_KEY_SIZE >> 2)
0027 #define CC_AES_256_BIT_KEY_SIZE 32
0028 #define CC_AES_256_BIT_KEY_SIZE_WORDS   (CC_AES_256_BIT_KEY_SIZE >> 2)
0029 #define CC_AES_KEY_SIZE_MAX         CC_AES_256_BIT_KEY_SIZE
0030 #define CC_AES_KEY_SIZE_WORDS_MAX       (CC_AES_KEY_SIZE_MAX >> 2)
0031
0032 #define CC_MD5_DIGEST_SIZE  16
0033 #define CC_SHA1_DIGEST_SIZE 20
0034 #define CC_SHA224_DIGEST_SIZE   28
0035 #define CC_SHA256_DIGEST_SIZE   32
0036 #define CC_SHA256_DIGEST_SIZE_IN_WORDS 8
0037 #define CC_SHA384_DIGEST_SIZE   48
0038 #define CC_SHA512_DIGEST_SIZE   64
0039
0040 #define CC_SHA1_BLOCK_SIZE 64
0041 #define CC_SHA1_BLOCK_SIZE_IN_WORDS 16
0042 #define CC_MD5_BLOCK_SIZE 64
0043 #define CC_MD5_BLOCK_SIZE_IN_WORDS 16
0044 #define CC_SHA224_BLOCK_SIZE 64
0045 #define CC_SHA256_BLOCK_SIZE 64
0046 #define CC_SHA256_BLOCK_SIZE_IN_WORDS 16
0047 #define CC_SHA1_224_256_BLOCK_SIZE 64
0048 #define CC_SHA384_BLOCK_SIZE 128
0049 #define CC_SHA512_BLOCK_SIZE 128
0050
0051 #define CC_DIGEST_SIZE_MAX CC_SHA512_DIGEST_SIZE
0052 #define CC_HASH_BLOCK_SIZE_MAX CC_SHA512_BLOCK_SIZE /*1024b*/
0053
0054 #define CC_HMAC_BLOCK_SIZE_MAX CC_HASH_BLOCK_SIZE_MAX
0055
0056 #define CC_DRV_ALG_MAX_BLOCK_SIZE CC_HASH_BLOCK_SIZE_MAX
0057
0058 #define CC_CPP_NUM_SLOTS    8
0059 #define CC_CPP_NUM_ALGS     2
0060
0061 enum cc_cpp_alg {
0062     CC_CPP_SM4 = 1,
0063     CC_CPP_AES = 0
0064 };
0065
0066 enum drv_engine_type {
0067     DRV_ENGINE_NULL = 0,
0068     DRV_ENGINE_AES = 1,
0069     DRV_ENGINE_DES = 2,
0070     DRV_ENGINE_HASH = 3,
0071     DRV_ENGINE_RC4 = 4,
0072     DRV_ENGINE_DOUT = 5,
0073     DRV_ENGINE_RESERVE32B = S32_MAX,
0074 };
0075
0076 enum drv_crypto_alg {
0077     DRV_CRYPTO_ALG_NULL = -1,
0078     DRV_CRYPTO_ALG_AES  = 0,
0079     DRV_CRYPTO_ALG_DES  = 1,
0080     DRV_CRYPTO_ALG_HASH = 2,
0081     DRV_CRYPTO_ALG_C2   = 3,
0082     DRV_CRYPTO_ALG_HMAC = 4,
0083     DRV_CRYPTO_ALG_AEAD = 5,
0084     DRV_CRYPTO_ALG_BYPASS = 6,
0085     DRV_CRYPTO_ALG_NUM = 7,
0086     DRV_CRYPTO_ALG_RESERVE32B = S32_MAX
0087 };
0088
0089 enum drv_crypto_direction {
0090     DRV_CRYPTO_DIRECTION_NULL = -1,
0091     DRV_CRYPTO_DIRECTION_ENCRYPT = 0,
0092     DRV_CRYPTO_DIRECTION_DECRYPT = 1,
0093     DRV_CRYPTO_DIRECTION_DECRYPT_ENCRYPT = 3,
0094     DRV_CRYPTO_DIRECTION_RESERVE32B = S32_MAX
0095 };
0096
0097 enum drv_cipher_mode {
0098     DRV_CIPHER_NULL_MODE = -1,
0099     DRV_CIPHER_ECB = 0,
0100     DRV_CIPHER_CBC = 1,
0101     DRV_CIPHER_CTR = 2,
0102     DRV_CIPHER_CBC_MAC = 3,
0103     DRV_CIPHER_XTS = 4,
0104     DRV_CIPHER_XCBC_MAC = 5,
0105     DRV_CIPHER_OFB = 6,
0106     DRV_CIPHER_CMAC = 7,
0107     DRV_CIPHER_CCM = 8,
0108     DRV_CIPHER_CBC_CTS = 11,
0109     DRV_CIPHER_GCTR = 12,
0110     DRV_CIPHER_ESSIV = 13,
0111     DRV_CIPHER_RESERVE32B = S32_MAX
0112 };
0113
0114 enum drv_hash_mode {
0115     DRV_HASH_NULL = -1,
0116     DRV_HASH_SHA1 = 0,
0117     DRV_HASH_SHA256 = 1,
0118     DRV_HASH_SHA224 = 2,
0119     DRV_HASH_SHA512 = 3,
0120     DRV_HASH_SHA384 = 4,
0121     DRV_HASH_MD5 = 5,
0122     DRV_HASH_CBC_MAC = 6,
0123     DRV_HASH_XCBC_MAC = 7,
0124     DRV_HASH_CMAC = 8,
0125     DRV_HASH_SM3 = 9,
0126     DRV_HASH_MODE_NUM = 10,
0127     DRV_HASH_RESERVE32B = S32_MAX
0128 };
0129
0130 enum drv_hash_hw_mode {
0131     DRV_HASH_HW_MD5 = 0,
0132     DRV_HASH_HW_SHA1 = 1,
0133     DRV_HASH_HW_SHA256 = 2,
0134     DRV_HASH_HW_SHA224 = 10,
0135     DRV_HASH_HW_SHA512 = 4,
0136     DRV_HASH_HW_SHA384 = 12,
0137     DRV_HASH_HW_GHASH = 6,
0138     DRV_HASH_HW_SM3 = 14,
0139     DRV_HASH_HW_RESERVE32B = S32_MAX
0140 };
0141
0142 #endif /* _CC_CRYPTO_CTX_H_ */