Back to home page

OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
0003 
0004 /* \file cc_aead.h
0005  * ARM CryptoCell AEAD Crypto API
0006  */
0007 
0008 #ifndef __CC_AEAD_H__
0009 #define __CC_AEAD_H__
0010 
0011 #include <linux/kernel.h>
0012 #include <crypto/algapi.h>
0013 #include <crypto/ctr.h>
0014 
0015 /* mac_cmp - HW writes 8 B but all bytes hold the same value */
0016 #define ICV_CMP_SIZE 8
0017 #define CCM_CONFIG_BUF_SIZE (AES_BLOCK_SIZE * 3)
0018 #define MAX_MAC_SIZE SHA256_DIGEST_SIZE
0019 
0020 /* defines for AES GCM configuration buffer */
0021 #define GCM_BLOCK_LEN_SIZE 8
0022 
0023 #define GCM_BLOCK_RFC4_IV_OFFSET    4
0024 #define GCM_BLOCK_RFC4_IV_SIZE      8  /* IV size for rfc's */
0025 #define GCM_BLOCK_RFC4_NONCE_OFFSET 0
0026 #define GCM_BLOCK_RFC4_NONCE_SIZE   4
0027 
0028 /* Offsets into AES CCM configuration buffer */
0029 #define CCM_B0_OFFSET 0
0030 #define CCM_A0_OFFSET 16
0031 #define CCM_CTR_COUNT_0_OFFSET 32
0032 /* CCM B0 and CTR_COUNT constants. */
0033 #define CCM_BLOCK_NONCE_OFFSET 1  /* Nonce offset inside B0 and CTR_COUNT */
0034 #define CCM_BLOCK_NONCE_SIZE   3  /* Nonce size inside B0 and CTR_COUNT */
0035 #define CCM_BLOCK_IV_OFFSET    4  /* IV offset inside B0 and CTR_COUNT */
0036 #define CCM_BLOCK_IV_SIZE      8  /* IV size inside B0 and CTR_COUNT */
0037 
0038 enum aead_ccm_header_size {
0039     ccm_header_size_null = -1,
0040     ccm_header_size_zero = 0,
0041     ccm_header_size_2 = 2,
0042     ccm_header_size_6 = 6,
0043     ccm_header_size_max = S32_MAX
0044 };
0045 
0046 struct aead_req_ctx {
0047     /* Allocate cache line although only 4 bytes are needed to
0048      *  assure next field falls @ cache line
0049      *  Used for both: digest HW compare and CCM/GCM MAC value
0050      */
0051     u8 mac_buf[MAX_MAC_SIZE] ____cacheline_aligned;
0052     u8 ctr_iv[AES_BLOCK_SIZE] ____cacheline_aligned;
0053 
0054     //used in gcm
0055     u8 gcm_iv_inc1[AES_BLOCK_SIZE] ____cacheline_aligned;
0056     u8 gcm_iv_inc2[AES_BLOCK_SIZE] ____cacheline_aligned;
0057     u8 hkey[AES_BLOCK_SIZE] ____cacheline_aligned;
0058     struct {
0059         u8 len_a[GCM_BLOCK_LEN_SIZE] ____cacheline_aligned;
0060         u8 len_c[GCM_BLOCK_LEN_SIZE];
0061     } gcm_len_block;
0062 
0063     u8 ccm_config[CCM_CONFIG_BUF_SIZE] ____cacheline_aligned;
0064     /* HW actual size input */
0065     unsigned int hw_iv_size ____cacheline_aligned;
0066     /* used to prevent cache coherence problem */
0067     u8 backup_mac[MAX_MAC_SIZE];
0068     u8 *backup_iv; /* store orig iv */
0069     u32 assoclen; /* size of AAD buffer to authenticate */
0070     dma_addr_t mac_buf_dma_addr; /* internal ICV DMA buffer */
0071     /* buffer for internal ccm configurations */
0072     dma_addr_t ccm_iv0_dma_addr;
0073     dma_addr_t icv_dma_addr; /* Phys. address of ICV */
0074 
0075     //used in gcm
0076     /* buffer for internal gcm configurations */
0077     dma_addr_t gcm_iv_inc1_dma_addr;
0078     /* buffer for internal gcm configurations */
0079     dma_addr_t gcm_iv_inc2_dma_addr;
0080     dma_addr_t hkey_dma_addr; /* Phys. address of hkey */
0081     dma_addr_t gcm_block_len_dma_addr; /* Phys. address of gcm block len */
0082 
0083     u8 *icv_virt_addr; /* Virt. address of ICV */
0084     struct async_gen_req_ctx gen_ctx;
0085     struct cc_mlli assoc;
0086     struct cc_mlli src;
0087     struct cc_mlli dst;
0088     struct scatterlist *src_sgl;
0089     struct scatterlist *dst_sgl;
0090     unsigned int src_offset;
0091     unsigned int dst_offset;
0092     enum cc_req_dma_buf_type assoc_buff_type;
0093     enum cc_req_dma_buf_type data_buff_type;
0094     struct mlli_params mlli_params;
0095     unsigned int cryptlen;
0096     struct scatterlist ccm_adata_sg;
0097     enum aead_ccm_header_size ccm_hdr_size;
0098     unsigned int req_authsize;
0099     enum drv_cipher_mode cipher_mode;
0100     bool is_icv_fragmented;
0101     bool is_single_pass;
0102     bool plaintext_authenticate_only; //for gcm_rfc4543
0103 };
0104 
0105 int cc_aead_alloc(struct cc_drvdata *drvdata);
0106 int cc_aead_free(struct cc_drvdata *drvdata);
0107 
0108 #endif /*__CC_AEAD_H__*/