cavium/cpt/cptvf.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2016 Cavium, Inc.
0004  */
0005
0006 #ifndef __CPTVF_H
0007 #define __CPTVF_H
0008
0009 #include <linux/list.h>
0010 #include "cpt_common.h"
0011
0012 /* Default command queue length */
0013 #define CPT_CMD_QLEN 2046
0014 #define CPT_CMD_QCHUNK_SIZE 1023
0015
0016 /* Default command timeout in seconds */
0017 #define CPT_COMMAND_TIMEOUT 4
0018 #define CPT_TIMER_THOLD 0xFFFF
0019 #define CPT_NUM_QS_PER_VF 1
0020 #define CPT_INST_SIZE 64
0021 #define CPT_NEXT_CHUNK_PTR_SIZE 8
0022
0023 #define CPT_VF_MSIX_VECTORS 2
0024 #define CPT_VF_INTR_MBOX_MASK BIT(0)
0025 #define CPT_VF_INTR_DOVF_MASK BIT(1)
0026 #define CPT_VF_INTR_IRDE_MASK BIT(2)
0027 #define CPT_VF_INTR_NWRP_MASK BIT(3)
0028 #define CPT_VF_INTR_SERR_MASK BIT(4)
0029 #define DMA_DIRECT_DIRECT 0 /* Input DIRECT, Output DIRECT */
0030 #define DMA_GATHER_SCATTER 1
0031 #define FROM_DPTR 1
0032
0033 /**
0034  * Enumeration cpt_vf_int_vec_e
0035  *
0036  * CPT VF MSI-X Vector Enumeration
0037  * Enumerates the MSI-X interrupt vectors.
0038  */
0039 enum cpt_vf_int_vec_e {
0040     CPT_VF_INT_VEC_E_MISC = 0x00,
0041     CPT_VF_INT_VEC_E_DONE = 0x01
0042 };
0043
0044 struct command_chunk {
0045     u8 *head;
0046     dma_addr_t dma_addr;
0047     u32 size; /* Chunk size, max CPT_INST_CHUNK_MAX_SIZE */
0048     struct hlist_node nextchunk;
0049 };
0050
0051 struct command_queue {
0052     spinlock_t lock; /* command queue lock */
0053     u32 idx; /* Command queue host write idx */
0054     u32 nchunks; /* Number of command chunks */
0055     struct command_chunk *qhead;    /* Command queue head, instructions
0056                      * are inserted here
0057                      */
0058     struct hlist_head chead;
0059 };
0060
0061 struct command_qinfo {
0062     u32 cmd_size;
0063     u32 qchunksize; /* Command queue chunk size */
0064     struct command_queue queue[CPT_NUM_QS_PER_VF];
0065 };
0066
0067 struct pending_entry {
0068     u8 busy; /* Entry status (free/busy) */
0069
0070     volatile u64 *completion_addr; /* Completion address */
0071     void *post_arg;
0072     void (*callback)(int, void *); /* Kernel ASYNC request callabck */
0073     void *callback_arg; /* Kernel ASYNC request callabck arg */
0074 };
0075
0076 struct pending_queue {
0077     struct pending_entry *head; /* head of the queue */
0078     u32 front; /* Process work from here */
0079     u32 rear; /* Append new work here */
0080     atomic64_t pending_count;
0081     spinlock_t lock; /* Queue lock */
0082 };
0083
0084 struct pending_qinfo {
0085     u32 nr_queues;  /* Number of queues supported */
0086     u32 qlen; /* Queue length */
0087     struct pending_queue queue[CPT_NUM_QS_PER_VF];
0088 };
0089
0090 #define for_each_pending_queue(qinfo, q, i) \
0091     for (i = 0, q = &qinfo->queue[i]; i < qinfo->nr_queues; i++, \
0092          q = &qinfo->queue[i])
0093
0094 struct cpt_vf {
0095     u16 flags; /* Flags to hold device status bits */
0096     u8 vfid; /* Device Index 0...CPT_MAX_VF_NUM */
0097     u8 vftype; /* VF type of SE_TYPE(1) or AE_TYPE(1) */
0098     u8 vfgrp; /* VF group (0 - 8) */
0099     u8 node; /* Operating node: Bits (46:44) in BAR0 address */
0100     u8 priority; /* VF priority ring: 1-High proirity round
0101               * robin ring;0-Low priority round robin ring;
0102               */
0103     struct pci_dev *pdev; /* pci device handle */
0104     void __iomem *reg_base; /* Register start address */
0105     void *wqe_info; /* BH worker info */
0106     /* MSI-X */
0107     cpumask_var_t affinity_mask[CPT_VF_MSIX_VECTORS];
0108     /* Command and Pending queues */
0109     u32 qsize;
0110     u32 nr_queues;
0111     struct command_qinfo cqinfo; /* Command queue information */
0112     struct pending_qinfo pqinfo; /* Pending queue information */
0113     /* VF-PF mailbox communication */
0114     bool pf_acked;
0115     bool pf_nacked;
0116 };
0117
0118 int cptvf_send_vf_up(struct cpt_vf *cptvf);
0119 int cptvf_send_vf_down(struct cpt_vf *cptvf);
0120 int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf);
0121 int cptvf_send_vf_priority_msg(struct cpt_vf *cptvf);
0122 int cptvf_send_vq_size_msg(struct cpt_vf *cptvf);
0123 int cptvf_check_pf_ready(struct cpt_vf *cptvf);
0124 void cptvf_handle_mbox_intr(struct cpt_vf *cptvf);
0125 void cvm_crypto_exit(void);
0126 int cvm_crypto_init(struct cpt_vf *cptvf);
0127 void vq_post_process(struct cpt_vf *cptvf, u32 qno);
0128 void cptvf_write_vq_doorbell(struct cpt_vf *cptvf, u32 val);
0129 #endif /* __CPTVF_H */