cavium/cpt/cptpf.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2016 Cavium, Inc.
0004  */
0005
0006 #ifndef __CPTPF_H
0007 #define __CPTPF_H
0008
0009 #include "cpt_common.h"
0010
0011 #define CSR_DELAY 30
0012 #define CPT_MAX_CORE_GROUPS 8
0013 #define CPT_MAX_SE_CORES 10
0014 #define CPT_MAX_AE_CORES 6
0015 #define CPT_MAX_TOTAL_CORES (CPT_MAX_SE_CORES + CPT_MAX_AE_CORES)
0016 #define CPT_MAX_VF_NUM 16
0017 #define CPT_PF_MSIX_VECTORS 3
0018 #define CPT_PF_INT_VEC_E_MBOXX(a) (0x02 + (a))
0019 #define CPT_UCODE_VERSION_SZ 32
0020 struct cpt_device;
0021
0022 struct microcode {
0023     u8 is_mc_valid;
0024     u8 is_ae;
0025     u8 group;
0026     u8 num_cores;
0027     u32 code_size;
0028     u64 core_mask;
0029     u8 version[CPT_UCODE_VERSION_SZ];
0030     /* Base info */
0031     dma_addr_t phys_base;
0032     void *code;
0033 };
0034
0035 struct cpt_vf_info {
0036     u8 state;
0037     u8 priority;
0038     u8 id;
0039     u32 qlen;
0040 };
0041
0042 /**
0043  * cpt device structure
0044  */
0045 struct cpt_device {
0046     u16 flags;  /* Flags to hold device status bits */
0047     u8 num_vf_en; /* Number of VFs enabled (0...CPT_MAX_VF_NUM) */
0048     struct cpt_vf_info vfinfo[CPT_MAX_VF_NUM]; /* Per VF info */
0049
0050     void __iomem *reg_base; /* Register start address */
0051     struct pci_dev *pdev; /* pci device handle */
0052
0053     struct microcode mcode[CPT_MAX_CORE_GROUPS];
0054     u8 next_mc_idx; /* next microcode index */
0055     u8 next_group;
0056     u8 max_se_cores;
0057     u8 max_ae_cores;
0058 };
0059
0060 void cpt_mbox_intr_handler(struct cpt_device *cpt, int mbx);
0061 #endif /* __CPTPF_H */