cavium/cpt/cpt_common.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2016 Cavium, Inc.
0004  */
0005
0006 #ifndef __CPT_COMMON_H
0007 #define __CPT_COMMON_H
0008
0009 #include <asm/byteorder.h>
0010 #include <linux/delay.h>
0011 #include <linux/pci.h>
0012
0013 #include "cpt_hw_types.h"
0014
0015 /* Device ID */
0016 #define CPT_81XX_PCI_PF_DEVICE_ID 0xa040
0017 #define CPT_81XX_PCI_VF_DEVICE_ID 0xa041
0018
0019 /* flags to indicate the features supported */
0020 #define CPT_FLAG_SRIOV_ENABLED BIT(1)
0021 #define CPT_FLAG_VF_DRIVER BIT(2)
0022 #define CPT_FLAG_DEVICE_READY BIT(3)
0023
0024 #define cpt_sriov_enabled(cpt) ((cpt)->flags & CPT_FLAG_SRIOV_ENABLED)
0025 #define cpt_vf_driver(cpt) ((cpt)->flags & CPT_FLAG_VF_DRIVER)
0026 #define cpt_device_ready(cpt) ((cpt)->flags & CPT_FLAG_DEVICE_READY)
0027
0028 #define CPT_MBOX_MSG_TYPE_ACK 1
0029 #define CPT_MBOX_MSG_TYPE_NACK 2
0030 #define CPT_MBOX_MSG_TIMEOUT 2000
0031 #define VF_STATE_DOWN 0
0032 #define VF_STATE_UP 1
0033
0034 /*
0035  * CPT Registers map for 81xx
0036  */
0037
0038 /* PF registers */
0039 #define CPTX_PF_CONSTANTS(a) (0x0ll + ((u64)(a) << 36))
0040 #define CPTX_PF_RESET(a) (0x100ll + ((u64)(a) << 36))
0041 #define CPTX_PF_DIAG(a) (0x120ll + ((u64)(a) << 36))
0042 #define CPTX_PF_BIST_STATUS(a) (0x160ll + ((u64)(a) << 36))
0043 #define CPTX_PF_ECC0_CTL(a) (0x200ll + ((u64)(a) << 36))
0044 #define CPTX_PF_ECC0_FLIP(a) (0x210ll + ((u64)(a) << 36))
0045 #define CPTX_PF_ECC0_INT(a) (0x220ll + ((u64)(a) << 36))
0046 #define CPTX_PF_ECC0_INT_W1S(a) (0x230ll + ((u64)(a) << 36))
0047 #define CPTX_PF_ECC0_ENA_W1S(a) (0x240ll + ((u64)(a) << 36))
0048 #define CPTX_PF_ECC0_ENA_W1C(a) (0x250ll + ((u64)(a) << 36))
0049 #define CPTX_PF_MBOX_INTX(a, b) \
0050     (0x400ll + ((u64)(a) << 36) + ((b) << 3))
0051 #define CPTX_PF_MBOX_INT_W1SX(a, b) \
0052     (0x420ll + ((u64)(a) << 36) + ((b) << 3))
0053 #define CPTX_PF_MBOX_ENA_W1CX(a, b) \
0054     (0x440ll + ((u64)(a) << 36) + ((b) << 3))
0055 #define CPTX_PF_MBOX_ENA_W1SX(a, b) \
0056     (0x460ll + ((u64)(a) << 36) + ((b) << 3))
0057 #define CPTX_PF_EXEC_INT(a) (0x500ll + 0x1000000000ll * ((a) & 0x1))
0058 #define CPTX_PF_EXEC_INT_W1S(a) (0x520ll + ((u64)(a) << 36))
0059 #define CPTX_PF_EXEC_ENA_W1C(a) (0x540ll + ((u64)(a) << 36))
0060 #define CPTX_PF_EXEC_ENA_W1S(a) (0x560ll + ((u64)(a) << 36))
0061 #define CPTX_PF_GX_EN(a, b) \
0062     (0x600ll + ((u64)(a) << 36) + ((b) << 3))
0063 #define CPTX_PF_EXEC_INFO(a) (0x700ll + ((u64)(a) << 36))
0064 #define CPTX_PF_EXEC_BUSY(a) (0x800ll + ((u64)(a) << 36))
0065 #define CPTX_PF_EXEC_INFO0(a) (0x900ll + ((u64)(a) << 36))
0066 #define CPTX_PF_EXEC_INFO1(a) (0x910ll + ((u64)(a) << 36))
0067 #define CPTX_PF_INST_REQ_PC(a) (0x10000ll + ((u64)(a) << 36))
0068 #define CPTX_PF_INST_LATENCY_PC(a) \
0069     (0x10020ll + ((u64)(a) << 36))
0070 #define CPTX_PF_RD_REQ_PC(a) (0x10040ll + ((u64)(a) << 36))
0071 #define CPTX_PF_RD_LATENCY_PC(a) (0x10060ll + ((u64)(a) << 36))
0072 #define CPTX_PF_RD_UC_PC(a) (0x10080ll + ((u64)(a) << 36))
0073 #define CPTX_PF_ACTIVE_CYCLES_PC(a) (0x10100ll + ((u64)(a) << 36))
0074 #define CPTX_PF_EXE_CTL(a) (0x4000000ll + ((u64)(a) << 36))
0075 #define CPTX_PF_EXE_STATUS(a) (0x4000008ll + ((u64)(a) << 36))
0076 #define CPTX_PF_EXE_CLK(a) (0x4000010ll + ((u64)(a) << 36))
0077 #define CPTX_PF_EXE_DBG_CTL(a) (0x4000018ll + ((u64)(a) << 36))
0078 #define CPTX_PF_EXE_DBG_DATA(a) (0x4000020ll + ((u64)(a) << 36))
0079 #define CPTX_PF_EXE_BIST_STATUS(a) (0x4000028ll + ((u64)(a) << 36))
0080 #define CPTX_PF_EXE_REQ_TIMER(a) (0x4000030ll + ((u64)(a) << 36))
0081 #define CPTX_PF_EXE_MEM_CTL(a) (0x4000038ll + ((u64)(a) << 36))
0082 #define CPTX_PF_EXE_PERF_CTL(a) (0x4001000ll + ((u64)(a) << 36))
0083 #define CPTX_PF_EXE_DBG_CNTX(a, b) \
0084     (0x4001100ll + ((u64)(a) << 36) + ((b) << 3))
0085 #define CPTX_PF_EXE_PERF_EVENT_CNT(a) (0x4001180ll + ((u64)(a) << 36))
0086 #define CPTX_PF_EXE_EPCI_INBX_CNT(a, b) \
0087     (0x4001200ll + ((u64)(a) << 36) + ((b) << 3))
0088 #define CPTX_PF_EXE_EPCI_OUTBX_CNT(a, b) \
0089     (0x4001240ll + ((u64)(a) << 36) + ((b) << 3))
0090 #define CPTX_PF_ENGX_UCODE_BASE(a, b) \
0091     (0x4002000ll + ((u64)(a) << 36) + ((b) << 3))
0092 #define CPTX_PF_QX_CTL(a, b) \
0093     (0x8000000ll + ((u64)(a) << 36) + ((b) << 20))
0094 #define CPTX_PF_QX_GMCTL(a, b) \
0095     (0x8000020ll + ((u64)(a) << 36) + ((b) << 20))
0096 #define CPTX_PF_QX_CTL2(a, b) \
0097     (0x8000100ll + ((u64)(a) << 36) + ((b) << 20))
0098 #define CPTX_PF_VFX_MBOXX(a, b, c) \
0099     (0x8001000ll + ((u64)(a) << 36) + ((b) << 20) + ((c) << 8))
0100
0101 /* VF registers */
0102 #define CPTX_VQX_CTL(a, b) (0x100ll + ((u64)(a) << 36) + ((b) << 20))
0103 #define CPTX_VQX_SADDR(a, b) (0x200ll + ((u64)(a) << 36) + ((b) << 20))
0104 #define CPTX_VQX_DONE_WAIT(a, b) (0x400ll + ((u64)(a) << 36) + ((b) << 20))
0105 #define CPTX_VQX_INPROG(a, b) (0x410ll + ((u64)(a) << 36) + ((b) << 20))
0106 #define CPTX_VQX_DONE(a, b) (0x420ll + ((u64)(a) << 36) + ((b) << 20))
0107 #define CPTX_VQX_DONE_ACK(a, b) (0x440ll + ((u64)(a) << 36) + ((b) << 20))
0108 #define CPTX_VQX_DONE_INT_W1S(a, b) (0x460ll + ((u64)(a) << 36) + ((b) << 20))
0109 #define CPTX_VQX_DONE_INT_W1C(a, b) (0x468ll + ((u64)(a) << 36) + ((b) << 20))
0110 #define CPTX_VQX_DONE_ENA_W1S(a, b) (0x470ll + ((u64)(a) << 36) + ((b) << 20))
0111 #define CPTX_VQX_DONE_ENA_W1C(a, b) (0x478ll + ((u64)(a) << 36) + ((b) << 20))
0112 #define CPTX_VQX_MISC_INT(a, b) (0x500ll + ((u64)(a) << 36) + ((b) << 20))
0113 #define CPTX_VQX_MISC_INT_W1S(a, b) (0x508ll + ((u64)(a) << 36) + ((b) << 20))
0114 #define CPTX_VQX_MISC_ENA_W1S(a, b) (0x510ll + ((u64)(a) << 36) + ((b) << 20))
0115 #define CPTX_VQX_MISC_ENA_W1C(a, b) (0x518ll + ((u64)(a) << 36) + ((b) << 20))
0116 #define CPTX_VQX_DOORBELL(a, b) (0x600ll + ((u64)(a) << 36) + ((b) << 20))
0117 #define CPTX_VFX_PF_MBOXX(a, b, c) \
0118     (0x1000ll + ((u64)(a) << 36) + ((b) << 20) + ((c) << 3))
0119
0120 enum vftype {
0121     AE_TYPES = 1,
0122     SE_TYPES = 2,
0123     BAD_CPT_TYPES,
0124 };
0125
0126 /* Max CPT devices supported */
0127 enum cpt_mbox_opcode {
0128     CPT_MSG_VF_UP = 1,
0129     CPT_MSG_VF_DOWN,
0130     CPT_MSG_READY,
0131     CPT_MSG_QLEN,
0132     CPT_MSG_QBIND_GRP,
0133     CPT_MSG_VQ_PRIORITY,
0134 };
0135
0136 /* CPT mailbox structure */
0137 struct cpt_mbox {
0138     u64 msg; /* Message type MBOX[0] */
0139     u64 data;/* Data         MBOX[1] */
0140 };
0141
0142 /* Register read/write APIs */
0143 static inline void cpt_write_csr64(u8 __iomem *hw_addr, u64 offset,
0144                    u64 val)
0145 {
0146     writeq(val, hw_addr + offset);
0147 }
0148
0149 static inline u64 cpt_read_csr64(u8 __iomem *hw_addr, u64 offset)
0150 {
0151     return readq(hw_addr + offset);
0152 }
0153 #endif /* __CPT_COMMON_H */