crypto/caam/intern.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * CAAM/SEC 4.x driver backend
0004  * Private/internal definitions between modules
0005  *
0006  * Copyright 2008-2011 Freescale Semiconductor, Inc.
0007  * Copyright 2019 NXP
0008  */
0009
0010 #ifndef INTERN_H
0011 #define INTERN_H
0012
0013 #include "ctrl.h"
0014 #include <crypto/engine.h>
0015
0016 /* Currently comes from Kconfig param as a ^2 (driver-required) */
0017 #define JOBR_DEPTH (1 << CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE)
0018
0019 /*
0020  * Maximum size for crypto-engine software queue based on Job Ring
0021  * size (JOBR_DEPTH) and a THRESHOLD (reserved for the non-crypto-API
0022  * requests that are not passed through crypto-engine)
0023  */
0024 #define THRESHOLD 15
0025 #define CRYPTO_ENGINE_MAX_QLEN (JOBR_DEPTH - THRESHOLD)
0026
0027 /* Kconfig params for interrupt coalescing if selected (else zero) */
0028 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_INTC
0029 #define JOBR_INTC JRCFG_ICEN
0030 #define JOBR_INTC_TIME_THLD CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_TIME_THLD
0031 #define JOBR_INTC_COUNT_THLD CONFIG_CRYPTO_DEV_FSL_CAAM_INTC_COUNT_THLD
0032 #else
0033 #define JOBR_INTC 0
0034 #define JOBR_INTC_TIME_THLD 0
0035 #define JOBR_INTC_COUNT_THLD 0
0036 #endif
0037
0038 /*
0039  * Storage for tracking each in-process entry moving across a ring
0040  * Each entry on an output ring needs one of these
0041  */
0042 struct caam_jrentry_info {
0043     void (*callbk)(struct device *dev, u32 *desc, u32 status, void *arg);
0044     void *cbkarg;   /* Argument per ring entry */
0045     u32 *desc_addr_virt;    /* Stored virt addr for postprocessing */
0046     dma_addr_t desc_addr_dma;   /* Stored bus addr for done matching */
0047     u32 desc_size;  /* Stored size for postprocessing, header derived */
0048 };
0049
0050 /* Private sub-storage for a single JobR */
0051 struct caam_drv_private_jr {
0052     struct list_head    list_node;  /* Job Ring device list */
0053     struct device       *dev;
0054     int ridx;
0055     struct caam_job_ring __iomem *rregs;    /* JobR's register space */
0056     struct tasklet_struct irqtask;
0057     int irq;            /* One per queue */
0058     bool hwrng;
0059
0060     /* Number of scatterlist crypt transforms active on the JobR */
0061     atomic_t tfm_count ____cacheline_aligned;
0062
0063     /* Job ring info */
0064     struct caam_jrentry_info *entinfo;  /* Alloc'ed 1 per ring entry */
0065     spinlock_t inplock ____cacheline_aligned; /* Input ring index lock */
0066     u32 inpring_avail;  /* Number of free entries in input ring */
0067     int head;           /* entinfo (s/w ring) head index */
0068     void *inpring;          /* Base of input ring, alloc
0069                      * DMA-safe */
0070     int out_ring_read_index;    /* Output index "tail" */
0071     int tail;           /* entinfo (s/w ring) tail index */
0072     void *outring;          /* Base of output ring, DMA-safe */
0073     struct crypto_engine *engine;
0074 };
0075
0076 /*
0077  * Driver-private storage for a single CAAM block instance
0078  */
0079 struct caam_drv_private {
0080     /* Physical-presence section */
0081     struct caam_ctrl __iomem *ctrl; /* controller region */
0082     struct caam_deco __iomem *deco; /* DECO/CCB views */
0083     struct caam_assurance __iomem *assure;
0084     struct caam_queue_if __iomem *qi; /* QI control region */
0085     struct caam_job_ring __iomem *jr[4];    /* JobR's register space */
0086
0087     struct iommu_domain *domain;
0088
0089     /*
0090      * Detected geometry block. Filled in from device tree if powerpc,
0091      * or from register-based version detection code
0092      */
0093     u8 total_jobrs;     /* Total Job Rings in device */
0094     u8 qi_present;      /* Nonzero if QI present in device */
0095     u8 blob_present;    /* Nonzero if BLOB support present in device */
0096     u8 mc_en;       /* Nonzero if MC f/w is active */
0097     int secvio_irq;     /* Security violation interrupt number */
0098     int virt_en;        /* Virtualization enabled in CAAM */
0099     int era;        /* CAAM Era (internal HW revision) */
0100
0101 #define RNG4_MAX_HANDLES 2
0102     /* RNG4 block */
0103     u32 rng4_sh_init;   /* This bitmap shows which of the State
0104                    Handles of the RNG4 block are initialized
0105                    by this driver */
0106
0107     struct clk_bulk_data *clks;
0108     int num_clks;
0109     /*
0110      * debugfs entries for developer view into driver/device
0111      * variables at runtime.
0112      */
0113 #ifdef CONFIG_DEBUG_FS
0114     struct dentry *ctl; /* controller dir */
0115     struct debugfs_blob_wrapper ctl_kek_wrap, ctl_tkek_wrap, ctl_tdsk_wrap;
0116 #endif
0117 };
0118
0119 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API
0120
0121 int caam_algapi_init(struct device *dev);
0122 void caam_algapi_exit(void);
0123
0124 #else
0125
0126 static inline int caam_algapi_init(struct device *dev)
0127 {
0128     return 0;
0129 }
0130
0131 static inline void caam_algapi_exit(void)
0132 {
0133 }
0134
0135 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API */
0136
0137 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API
0138
0139 int caam_algapi_hash_init(struct device *dev);
0140 void caam_algapi_hash_exit(void);
0141
0142 #else
0143
0144 static inline int caam_algapi_hash_init(struct device *dev)
0145 {
0146     return 0;
0147 }
0148
0149 static inline void caam_algapi_hash_exit(void)
0150 {
0151 }
0152
0153 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API */
0154
0155 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API
0156
0157 int caam_pkc_init(struct device *dev);
0158 void caam_pkc_exit(void);
0159
0160 #else
0161
0162 static inline int caam_pkc_init(struct device *dev)
0163 {
0164     return 0;
0165 }
0166
0167 static inline void caam_pkc_exit(void)
0168 {
0169 }
0170
0171 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API */
0172
0173 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API
0174
0175 int caam_rng_init(struct device *dev);
0176 void caam_rng_exit(struct device *dev);
0177
0178 #else
0179
0180 static inline int caam_rng_init(struct device *dev)
0181 {
0182     return 0;
0183 }
0184
0185 static inline void caam_rng_exit(struct device *dev) {}
0186
0187 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API */
0188
0189 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API
0190
0191 int caam_prng_register(struct device *dev);
0192 void caam_prng_unregister(void *data);
0193
0194 #else
0195
0196 static inline int caam_prng_register(struct device *dev)
0197 {
0198     return 0;
0199 }
0200
0201 static inline void caam_prng_unregister(void *data) {}
0202 #endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API */
0203
0204 #ifdef CONFIG_CAAM_QI
0205
0206 int caam_qi_algapi_init(struct device *dev);
0207 void caam_qi_algapi_exit(void);
0208
0209 #else
0210
0211 static inline int caam_qi_algapi_init(struct device *dev)
0212 {
0213     return 0;
0214 }
0215
0216 static inline void caam_qi_algapi_exit(void)
0217 {
0218 }
0219
0220 #endif /* CONFIG_CAAM_QI */
0221
0222 static inline u64 caam_get_dma_mask(struct device *dev)
0223 {
0224     struct device_node *nprop = dev->of_node;
0225
0226     if (caam_ptr_sz != sizeof(u64))
0227         return DMA_BIT_MASK(32);
0228
0229     if (caam_dpaa2)
0230         return DMA_BIT_MASK(49);
0231
0232     if (of_device_is_compatible(nprop, "fsl,sec-v5.0-job-ring") ||
0233         of_device_is_compatible(nprop, "fsl,sec-v5.0"))
0234         return DMA_BIT_MASK(40);
0235
0236     return DMA_BIT_MASK(36);
0237 }
0238
0239
0240 #endif /* INTERN_H */