crypto/caam/dpseci_cmd.h

0001 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
0002 /*
0003  * Copyright 2013-2016 Freescale Semiconductor Inc.
0004  * Copyright 2017-2018 NXP
0005  */
0006
0007 #ifndef _DPSECI_CMD_H_
0008 #define _DPSECI_CMD_H_
0009
0010 /* DPSECI Version */
0011 #define DPSECI_VER_MAJOR                5
0012 #define DPSECI_VER_MINOR                3
0013
0014 #define DPSECI_VER(maj, min)    (((maj) << 16) | (min))
0015 #define DPSECI_VERSION      DPSECI_VER(DPSECI_VER_MAJOR, DPSECI_VER_MINOR)
0016
0017 /* Command versioning */
0018 #define DPSECI_CMD_BASE_VERSION     1
0019 #define DPSECI_CMD_BASE_VERSION_V2  2
0020 #define DPSECI_CMD_ID_OFFSET        4
0021
0022 #define DPSECI_CMD_V1(id)   (((id) << DPSECI_CMD_ID_OFFSET) | \
0023                  DPSECI_CMD_BASE_VERSION)
0024
0025 #define DPSECI_CMD_V2(id)   (((id) << DPSECI_CMD_ID_OFFSET) | \
0026                  DPSECI_CMD_BASE_VERSION_V2)
0027
0028 /* Command IDs */
0029 #define DPSECI_CMDID_CLOSE              DPSECI_CMD_V1(0x800)
0030 #define DPSECI_CMDID_OPEN               DPSECI_CMD_V1(0x809)
0031 #define DPSECI_CMDID_GET_API_VERSION            DPSECI_CMD_V1(0xa09)
0032
0033 #define DPSECI_CMDID_ENABLE             DPSECI_CMD_V1(0x002)
0034 #define DPSECI_CMDID_DISABLE                DPSECI_CMD_V1(0x003)
0035 #define DPSECI_CMDID_GET_ATTR               DPSECI_CMD_V1(0x004)
0036 #define DPSECI_CMDID_RESET              DPSECI_CMD_V1(0x005)
0037 #define DPSECI_CMDID_IS_ENABLED             DPSECI_CMD_V1(0x006)
0038
0039 #define DPSECI_CMDID_SET_RX_QUEUE           DPSECI_CMD_V1(0x194)
0040 #define DPSECI_CMDID_GET_RX_QUEUE           DPSECI_CMD_V1(0x196)
0041 #define DPSECI_CMDID_GET_TX_QUEUE           DPSECI_CMD_V1(0x197)
0042 #define DPSECI_CMDID_GET_SEC_ATTR           DPSECI_CMD_V2(0x198)
0043 #define DPSECI_CMDID_SET_CONGESTION_NOTIFICATION    DPSECI_CMD_V1(0x170)
0044 #define DPSECI_CMDID_GET_CONGESTION_NOTIFICATION    DPSECI_CMD_V1(0x171)
0045
0046 /* Macros for accessing command fields smaller than 1 byte */
0047 #define DPSECI_MASK(field)  \
0048     GENMASK(DPSECI_##field##_SHIFT + DPSECI_##field##_SIZE - 1, \
0049         DPSECI_##field##_SHIFT)
0050
0051 #define dpseci_set_field(var, field, val)   \
0052     ((var) |= (((val) << DPSECI_##field##_SHIFT) & DPSECI_MASK(field)))
0053
0054 #define dpseci_get_field(var, field)    \
0055     (((var) & DPSECI_MASK(field)) >> DPSECI_##field##_SHIFT)
0056
0057 struct dpseci_cmd_open {
0058     __le32 dpseci_id;
0059 };
0060
0061 #define DPSECI_ENABLE_SHIFT 0
0062 #define DPSECI_ENABLE_SIZE  1
0063
0064 struct dpseci_rsp_is_enabled {
0065     u8 is_enabled;
0066 };
0067
0068 struct dpseci_rsp_get_attributes {
0069     __le32 id;
0070     __le32 pad0;
0071     u8 num_tx_queues;
0072     u8 num_rx_queues;
0073     u8 pad1[6];
0074     __le32 options;
0075 };
0076
0077 #define DPSECI_DEST_TYPE_SHIFT  0
0078 #define DPSECI_DEST_TYPE_SIZE   4
0079
0080 #define DPSECI_ORDER_PRESERVATION_SHIFT 0
0081 #define DPSECI_ORDER_PRESERVATION_SIZE  1
0082
0083 struct dpseci_cmd_queue {
0084     __le32 dest_id;
0085     u8 priority;
0086     u8 queue;
0087     u8 dest_type;
0088     u8 pad;
0089     __le64 user_ctx;
0090     union {
0091         __le32 options;
0092         __le32 fqid;
0093     };
0094     u8 order_preservation_en;
0095 };
0096
0097 struct dpseci_rsp_get_tx_queue {
0098     __le32 pad;
0099     __le32 fqid;
0100     u8 priority;
0101 };
0102
0103 struct dpseci_rsp_get_sec_attr {
0104     __le16 ip_id;
0105     u8 major_rev;
0106     u8 minor_rev;
0107     u8 era;
0108     u8 pad0[3];
0109     u8 deco_num;
0110     u8 zuc_auth_acc_num;
0111     u8 zuc_enc_acc_num;
0112     u8 pad1;
0113     u8 snow_f8_acc_num;
0114     u8 snow_f9_acc_num;
0115     u8 crc_acc_num;
0116     u8 pad2;
0117     u8 pk_acc_num;
0118     u8 kasumi_acc_num;
0119     u8 rng_acc_num;
0120     u8 pad3;
0121     u8 md_acc_num;
0122     u8 arc4_acc_num;
0123     u8 des_acc_num;
0124     u8 aes_acc_num;
0125     u8 ccha_acc_num;
0126     u8 ptha_acc_num;
0127 };
0128
0129 struct dpseci_rsp_get_api_version {
0130     __le16 major;
0131     __le16 minor;
0132 };
0133
0134 #define DPSECI_CGN_DEST_TYPE_SHIFT  0
0135 #define DPSECI_CGN_DEST_TYPE_SIZE   4
0136 #define DPSECI_CGN_UNITS_SHIFT      4
0137 #define DPSECI_CGN_UNITS_SIZE       2
0138
0139 struct dpseci_cmd_congestion_notification {
0140     __le32 dest_id;
0141     __le16 notification_mode;
0142     u8 priority;
0143     u8 options;
0144     __le64 message_iova;
0145     __le64 message_ctx;
0146     __le32 threshold_entry;
0147     __le32 threshold_exit;
0148 };
0149
0150 #endif /* _DPSECI_CMD_H_ */