crypto/caam/caamalg_qi2.h

0001 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
0002 /*
0003  * Copyright 2015-2016 Freescale Semiconductor Inc.
0004  * Copyright 2017-2018 NXP
0005  */
0006
0007 #ifndef _CAAMALG_QI2_H_
0008 #define _CAAMALG_QI2_H_
0009
0010 #include <soc/fsl/dpaa2-io.h>
0011 #include <soc/fsl/dpaa2-fd.h>
0012 #include <linux/threads.h>
0013 #include <linux/netdevice.h>
0014 #include "dpseci.h"
0015 #include "desc_constr.h"
0016 #include <crypto/skcipher.h>
0017
0018 #define DPAA2_CAAM_STORE_SIZE   16
0019 /* NAPI weight *must* be a multiple of the store size. */
0020 #define DPAA2_CAAM_NAPI_WEIGHT  512
0021
0022 /* The congestion entrance threshold was chosen so that on LS2088
0023  * we support the maximum throughput for the available memory
0024  */
0025 #define DPAA2_SEC_CONG_ENTRY_THRESH (128 * 1024 * 1024)
0026 #define DPAA2_SEC_CONG_EXIT_THRESH  (DPAA2_SEC_CONG_ENTRY_THRESH * 9 / 10)
0027
0028 /**
0029  * dpaa2_caam_priv - driver private data
0030  * @dpseci_id: DPSECI object unique ID
0031  * @major_ver: DPSECI major version
0032  * @minor_ver: DPSECI minor version
0033  * @dpseci_attr: DPSECI attributes
0034  * @sec_attr: SEC engine attributes
0035  * @rx_queue_attr: array of Rx queue attributes
0036  * @tx_queue_attr: array of Tx queue attributes
0037  * @cscn_mem: pointer to memory region containing the congestion SCN
0038  *  it's size is larger than to accommodate alignment
0039  * @cscn_mem_aligned: pointer to congestion SCN; it is computed as
0040  *  PTR_ALIGN(cscn_mem, DPAA2_CSCN_ALIGN)
0041  * @cscn_dma: dma address used by the QMAN to write CSCN messages
0042  * @dev: device associated with the DPSECI object
0043  * @mc_io: pointer to MC portal's I/O object
0044  * @domain: IOMMU domain
0045  * @ppriv: per CPU pointers to privata data
0046  */
0047 struct dpaa2_caam_priv {
0048     int dpsec_id;
0049
0050     u16 major_ver;
0051     u16 minor_ver;
0052
0053     struct dpseci_attr dpseci_attr;
0054     struct dpseci_sec_attr sec_attr;
0055     struct dpseci_rx_queue_attr rx_queue_attr[DPSECI_MAX_QUEUE_NUM];
0056     struct dpseci_tx_queue_attr tx_queue_attr[DPSECI_MAX_QUEUE_NUM];
0057     int num_pairs;
0058
0059     /* congestion */
0060     void *cscn_mem;
0061     void *cscn_mem_aligned;
0062     dma_addr_t cscn_dma;
0063
0064     struct device *dev;
0065     struct fsl_mc_io *mc_io;
0066     struct iommu_domain *domain;
0067
0068     struct dpaa2_caam_priv_per_cpu __percpu *ppriv;
0069     struct dentry *dfs_root;
0070 };
0071
0072 /**
0073  * dpaa2_caam_priv_per_cpu - per CPU private data
0074  * @napi: napi structure
0075  * @net_dev: netdev used by napi
0076  * @req_fqid: (virtual) request (Tx / enqueue) FQID
0077  * @rsp_fqid: (virtual) response (Rx / dequeue) FQID
0078  * @prio: internal queue number - index for dpaa2_caam_priv.*_queue_attr
0079  * @nctx: notification context of response FQ
0080  * @store: where dequeued frames are stored
0081  * @priv: backpointer to dpaa2_caam_priv
0082  * @dpio: portal used for data path operations
0083  */
0084 struct dpaa2_caam_priv_per_cpu {
0085     struct napi_struct napi;
0086     struct net_device net_dev;
0087     int req_fqid;
0088     int rsp_fqid;
0089     int prio;
0090     struct dpaa2_io_notification_ctx nctx;
0091     struct dpaa2_io_store *store;
0092     struct dpaa2_caam_priv *priv;
0093     struct dpaa2_io *dpio;
0094 };
0095
0096 /* Length of a single buffer in the QI driver memory cache */
0097 #define CAAM_QI_MEMCACHE_SIZE   512
0098
0099 /*
0100  * aead_edesc - s/w-extended aead descriptor
0101  * @src_nents: number of segments in input scatterlist
0102  * @dst_nents: number of segments in output scatterlist
0103  * @iv_dma: dma address of iv for checking continuity and link table
0104  * @qm_sg_bytes: length of dma mapped h/w link table
0105  * @qm_sg_dma: bus physical mapped address of h/w link table
0106  * @assoclen: associated data length, in CAAM endianness
0107  * @assoclen_dma: bus physical mapped address of req->assoclen
0108  * @sgt: the h/w link table, followed by IV
0109  */
0110 struct aead_edesc {
0111     int src_nents;
0112     int dst_nents;
0113     dma_addr_t iv_dma;
0114     int qm_sg_bytes;
0115     dma_addr_t qm_sg_dma;
0116     unsigned int assoclen;
0117     dma_addr_t assoclen_dma;
0118     struct dpaa2_sg_entry sgt[];
0119 };
0120
0121 /*
0122  * skcipher_edesc - s/w-extended skcipher descriptor
0123  * @src_nents: number of segments in input scatterlist
0124  * @dst_nents: number of segments in output scatterlist
0125  * @iv_dma: dma address of iv for checking continuity and link table
0126  * @qm_sg_bytes: length of dma mapped qm_sg space
0127  * @qm_sg_dma: I/O virtual address of h/w link table
0128  * @sgt: the h/w link table, followed by IV
0129  */
0130 struct skcipher_edesc {
0131     int src_nents;
0132     int dst_nents;
0133     dma_addr_t iv_dma;
0134     int qm_sg_bytes;
0135     dma_addr_t qm_sg_dma;
0136     struct dpaa2_sg_entry sgt[];
0137 };
0138
0139 /*
0140  * ahash_edesc - s/w-extended ahash descriptor
0141  * @qm_sg_dma: I/O virtual address of h/w link table
0142  * @src_nents: number of segments in input scatterlist
0143  * @qm_sg_bytes: length of dma mapped qm_sg space
0144  * @sgt: pointer to h/w link table
0145  */
0146 struct ahash_edesc {
0147     dma_addr_t qm_sg_dma;
0148     int src_nents;
0149     int qm_sg_bytes;
0150     struct dpaa2_sg_entry sgt[];
0151 };
0152
0153 /**
0154  * caam_flc - Flow Context (FLC)
0155  * @flc: Flow Context options
0156  * @sh_desc: Shared Descriptor
0157  */
0158 struct caam_flc {
0159     u32 flc[16];
0160     u32 sh_desc[MAX_SDLEN];
0161 } ____cacheline_aligned;
0162
0163 enum optype {
0164     ENCRYPT = 0,
0165     DECRYPT,
0166     NUM_OP
0167 };
0168
0169 /**
0170  * caam_request - the request structure the driver application should fill while
0171  *                submitting a job to driver.
0172  * @fd_flt: Frame list table defining input and output
0173  *          fd_flt[0] - FLE pointing to output buffer
0174  *          fd_flt[1] - FLE pointing to input buffer
0175  * @fd_flt_dma: DMA address for the frame list table
0176  * @flc: Flow Context
0177  * @flc_dma: I/O virtual address of Flow Context
0178  * @cbk: Callback function to invoke when job is completed
0179  * @ctx: arbit context attached with request by the application
0180  * @edesc: extended descriptor; points to one of {skcipher,aead}_edesc
0181  */
0182 struct caam_request {
0183     struct dpaa2_fl_entry fd_flt[2];
0184     dma_addr_t fd_flt_dma;
0185     struct caam_flc *flc;
0186     dma_addr_t flc_dma;
0187     void (*cbk)(void *ctx, u32 err);
0188     void *ctx;
0189     void *edesc;
0190     struct skcipher_request fallback_req;
0191 };
0192
0193 /**
0194  * dpaa2_caam_enqueue() - enqueue a crypto request
0195  * @dev: device associated with the DPSECI object
0196  * @req: pointer to caam_request
0197  */
0198 int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req);
0199
0200 #endif  /* _CAAMALG_QI2_H_ */