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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Cryptographic API.
0004  *
0005  * Support for ATMEL DES/TDES HW acceleration.
0006  *
0007  * Copyright (c) 2012 Eukréa Electromatique - ATMEL
0008  * Author: Nicolas Royer <nicolas@eukrea.com>
0009  *
0010  * Some ideas are from omap-aes.c drivers.
0011  */
0012 
0013 
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/slab.h>
0017 #include <linux/err.h>
0018 #include <linux/clk.h>
0019 #include <linux/io.h>
0020 #include <linux/hw_random.h>
0021 #include <linux/platform_device.h>
0022 
0023 #include <linux/device.h>
0024 #include <linux/dmaengine.h>
0025 #include <linux/init.h>
0026 #include <linux/errno.h>
0027 #include <linux/interrupt.h>
0028 #include <linux/irq.h>
0029 #include <linux/scatterlist.h>
0030 #include <linux/dma-mapping.h>
0031 #include <linux/of_device.h>
0032 #include <linux/delay.h>
0033 #include <linux/crypto.h>
0034 #include <crypto/scatterwalk.h>
0035 #include <crypto/algapi.h>
0036 #include <crypto/internal/des.h>
0037 #include <crypto/internal/skcipher.h>
0038 #include "atmel-tdes-regs.h"
0039 
0040 #define ATMEL_TDES_PRIORITY 300
0041 
0042 /* TDES flags  */
0043 /* Reserve bits [17:16], [13:12], [2:0] for AES Mode Register */
0044 #define TDES_FLAGS_ENCRYPT  TDES_MR_CYPHER_ENC
0045 #define TDES_FLAGS_OPMODE_MASK  (TDES_MR_OPMOD_MASK | TDES_MR_CFBS_MASK)
0046 #define TDES_FLAGS_ECB      TDES_MR_OPMOD_ECB
0047 #define TDES_FLAGS_CBC      TDES_MR_OPMOD_CBC
0048 #define TDES_FLAGS_OFB      TDES_MR_OPMOD_OFB
0049 #define TDES_FLAGS_CFB64    (TDES_MR_OPMOD_CFB | TDES_MR_CFBS_64b)
0050 #define TDES_FLAGS_CFB32    (TDES_MR_OPMOD_CFB | TDES_MR_CFBS_32b)
0051 #define TDES_FLAGS_CFB16    (TDES_MR_OPMOD_CFB | TDES_MR_CFBS_16b)
0052 #define TDES_FLAGS_CFB8     (TDES_MR_OPMOD_CFB | TDES_MR_CFBS_8b)
0053 
0054 #define TDES_FLAGS_MODE_MASK    (TDES_FLAGS_OPMODE_MASK | TDES_FLAGS_ENCRYPT)
0055 
0056 #define TDES_FLAGS_INIT     BIT(3)
0057 #define TDES_FLAGS_FAST     BIT(4)
0058 #define TDES_FLAGS_BUSY     BIT(5)
0059 #define TDES_FLAGS_DMA      BIT(6)
0060 
0061 #define ATMEL_TDES_QUEUE_LENGTH 50
0062 
0063 #define CFB8_BLOCK_SIZE     1
0064 #define CFB16_BLOCK_SIZE    2
0065 #define CFB32_BLOCK_SIZE    4
0066 
0067 struct atmel_tdes_caps {
0068     bool    has_dma;
0069     u32     has_cfb_3keys;
0070 };
0071 
0072 struct atmel_tdes_dev;
0073 
0074 struct atmel_tdes_ctx {
0075     struct atmel_tdes_dev *dd;
0076 
0077     int     keylen;
0078     u32     key[DES3_EDE_KEY_SIZE / sizeof(u32)];
0079     unsigned long   flags;
0080 
0081     u16     block_size;
0082 };
0083 
0084 struct atmel_tdes_reqctx {
0085     unsigned long mode;
0086     u8 lastc[DES_BLOCK_SIZE];
0087 };
0088 
0089 struct atmel_tdes_dma {
0090     struct dma_chan         *chan;
0091     struct dma_slave_config dma_conf;
0092 };
0093 
0094 struct atmel_tdes_dev {
0095     struct list_head    list;
0096     unsigned long       phys_base;
0097     void __iomem        *io_base;
0098 
0099     struct atmel_tdes_ctx   *ctx;
0100     struct device       *dev;
0101     struct clk          *iclk;
0102     int                 irq;
0103 
0104     unsigned long       flags;
0105 
0106     spinlock_t      lock;
0107     struct crypto_queue queue;
0108 
0109     struct tasklet_struct   done_task;
0110     struct tasklet_struct   queue_task;
0111 
0112     struct skcipher_request *req;
0113     size_t              total;
0114 
0115     struct scatterlist  *in_sg;
0116     unsigned int        nb_in_sg;
0117     size_t              in_offset;
0118     struct scatterlist  *out_sg;
0119     unsigned int        nb_out_sg;
0120     size_t              out_offset;
0121 
0122     size_t  buflen;
0123     size_t  dma_size;
0124 
0125     void    *buf_in;
0126     int     dma_in;
0127     dma_addr_t  dma_addr_in;
0128     struct atmel_tdes_dma   dma_lch_in;
0129 
0130     void    *buf_out;
0131     int     dma_out;
0132     dma_addr_t  dma_addr_out;
0133     struct atmel_tdes_dma   dma_lch_out;
0134 
0135     struct atmel_tdes_caps  caps;
0136 
0137     u32 hw_version;
0138 };
0139 
0140 struct atmel_tdes_drv {
0141     struct list_head    dev_list;
0142     spinlock_t      lock;
0143 };
0144 
0145 static struct atmel_tdes_drv atmel_tdes = {
0146     .dev_list = LIST_HEAD_INIT(atmel_tdes.dev_list),
0147     .lock = __SPIN_LOCK_UNLOCKED(atmel_tdes.lock),
0148 };
0149 
0150 static int atmel_tdes_sg_copy(struct scatterlist **sg, size_t *offset,
0151             void *buf, size_t buflen, size_t total, int out)
0152 {
0153     size_t count, off = 0;
0154 
0155     while (buflen && total) {
0156         count = min((*sg)->length - *offset, total);
0157         count = min(count, buflen);
0158 
0159         if (!count)
0160             return off;
0161 
0162         scatterwalk_map_and_copy(buf + off, *sg, *offset, count, out);
0163 
0164         off += count;
0165         buflen -= count;
0166         *offset += count;
0167         total -= count;
0168 
0169         if (*offset == (*sg)->length) {
0170             *sg = sg_next(*sg);
0171             if (*sg)
0172                 *offset = 0;
0173             else
0174                 total = 0;
0175         }
0176     }
0177 
0178     return off;
0179 }
0180 
0181 static inline u32 atmel_tdes_read(struct atmel_tdes_dev *dd, u32 offset)
0182 {
0183     return readl_relaxed(dd->io_base + offset);
0184 }
0185 
0186 static inline void atmel_tdes_write(struct atmel_tdes_dev *dd,
0187                     u32 offset, u32 value)
0188 {
0189     writel_relaxed(value, dd->io_base + offset);
0190 }
0191 
0192 static void atmel_tdes_write_n(struct atmel_tdes_dev *dd, u32 offset,
0193                    const u32 *value, int count)
0194 {
0195     for (; count--; value++, offset += 4)
0196         atmel_tdes_write(dd, offset, *value);
0197 }
0198 
0199 static struct atmel_tdes_dev *atmel_tdes_dev_alloc(void)
0200 {
0201     struct atmel_tdes_dev *tdes_dd;
0202 
0203     spin_lock_bh(&atmel_tdes.lock);
0204     /* One TDES IP per SoC. */
0205     tdes_dd = list_first_entry_or_null(&atmel_tdes.dev_list,
0206                        struct atmel_tdes_dev, list);
0207     spin_unlock_bh(&atmel_tdes.lock);
0208     return tdes_dd;
0209 }
0210 
0211 static int atmel_tdes_hw_init(struct atmel_tdes_dev *dd)
0212 {
0213     int err;
0214 
0215     err = clk_prepare_enable(dd->iclk);
0216     if (err)
0217         return err;
0218 
0219     if (!(dd->flags & TDES_FLAGS_INIT)) {
0220         atmel_tdes_write(dd, TDES_CR, TDES_CR_SWRST);
0221         dd->flags |= TDES_FLAGS_INIT;
0222     }
0223 
0224     return 0;
0225 }
0226 
0227 static inline unsigned int atmel_tdes_get_version(struct atmel_tdes_dev *dd)
0228 {
0229     return atmel_tdes_read(dd, TDES_HW_VERSION) & 0x00000fff;
0230 }
0231 
0232 static int atmel_tdes_hw_version_init(struct atmel_tdes_dev *dd)
0233 {
0234     int err;
0235 
0236     err = atmel_tdes_hw_init(dd);
0237     if (err)
0238         return err;
0239 
0240     dd->hw_version = atmel_tdes_get_version(dd);
0241 
0242     dev_info(dd->dev,
0243             "version: 0x%x\n", dd->hw_version);
0244 
0245     clk_disable_unprepare(dd->iclk);
0246 
0247     return 0;
0248 }
0249 
0250 static void atmel_tdes_dma_callback(void *data)
0251 {
0252     struct atmel_tdes_dev *dd = data;
0253 
0254     /* dma_lch_out - completed */
0255     tasklet_schedule(&dd->done_task);
0256 }
0257 
0258 static int atmel_tdes_write_ctrl(struct atmel_tdes_dev *dd)
0259 {
0260     int err;
0261     u32 valmr = TDES_MR_SMOD_PDC;
0262 
0263     err = atmel_tdes_hw_init(dd);
0264 
0265     if (err)
0266         return err;
0267 
0268     if (!dd->caps.has_dma)
0269         atmel_tdes_write(dd, TDES_PTCR,
0270             TDES_PTCR_TXTDIS | TDES_PTCR_RXTDIS);
0271 
0272     /* MR register must be set before IV registers */
0273     if (dd->ctx->keylen > (DES_KEY_SIZE << 1)) {
0274         valmr |= TDES_MR_KEYMOD_3KEY;
0275         valmr |= TDES_MR_TDESMOD_TDES;
0276     } else if (dd->ctx->keylen > DES_KEY_SIZE) {
0277         valmr |= TDES_MR_KEYMOD_2KEY;
0278         valmr |= TDES_MR_TDESMOD_TDES;
0279     } else {
0280         valmr |= TDES_MR_TDESMOD_DES;
0281     }
0282 
0283     valmr |= dd->flags & TDES_FLAGS_MODE_MASK;
0284 
0285     atmel_tdes_write(dd, TDES_MR, valmr);
0286 
0287     atmel_tdes_write_n(dd, TDES_KEY1W1R, dd->ctx->key,
0288                         dd->ctx->keylen >> 2);
0289 
0290     if (dd->req->iv && (valmr & TDES_MR_OPMOD_MASK) != TDES_MR_OPMOD_ECB)
0291         atmel_tdes_write_n(dd, TDES_IV1R, (void *)dd->req->iv, 2);
0292 
0293     return 0;
0294 }
0295 
0296 static int atmel_tdes_crypt_pdc_stop(struct atmel_tdes_dev *dd)
0297 {
0298     int err = 0;
0299     size_t count;
0300 
0301     atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS);
0302 
0303     if (dd->flags & TDES_FLAGS_FAST) {
0304         dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
0305         dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
0306     } else {
0307         dma_sync_single_for_device(dd->dev, dd->dma_addr_out,
0308                        dd->dma_size, DMA_FROM_DEVICE);
0309 
0310         /* copy data */
0311         count = atmel_tdes_sg_copy(&dd->out_sg, &dd->out_offset,
0312                 dd->buf_out, dd->buflen, dd->dma_size, 1);
0313         if (count != dd->dma_size) {
0314             err = -EINVAL;
0315             dev_dbg(dd->dev, "not all data converted: %zu\n", count);
0316         }
0317     }
0318 
0319     return err;
0320 }
0321 
0322 static int atmel_tdes_buff_init(struct atmel_tdes_dev *dd)
0323 {
0324     int err = -ENOMEM;
0325 
0326     dd->buf_in = (void *)__get_free_pages(GFP_KERNEL, 0);
0327     dd->buf_out = (void *)__get_free_pages(GFP_KERNEL, 0);
0328     dd->buflen = PAGE_SIZE;
0329     dd->buflen &= ~(DES_BLOCK_SIZE - 1);
0330 
0331     if (!dd->buf_in || !dd->buf_out) {
0332         dev_dbg(dd->dev, "unable to alloc pages.\n");
0333         goto err_alloc;
0334     }
0335 
0336     /* MAP here */
0337     dd->dma_addr_in = dma_map_single(dd->dev, dd->buf_in,
0338                     dd->buflen, DMA_TO_DEVICE);
0339     err = dma_mapping_error(dd->dev, dd->dma_addr_in);
0340     if (err) {
0341         dev_dbg(dd->dev, "dma %zd bytes error\n", dd->buflen);
0342         goto err_map_in;
0343     }
0344 
0345     dd->dma_addr_out = dma_map_single(dd->dev, dd->buf_out,
0346                     dd->buflen, DMA_FROM_DEVICE);
0347     err = dma_mapping_error(dd->dev, dd->dma_addr_out);
0348     if (err) {
0349         dev_dbg(dd->dev, "dma %zd bytes error\n", dd->buflen);
0350         goto err_map_out;
0351     }
0352 
0353     return 0;
0354 
0355 err_map_out:
0356     dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen,
0357         DMA_TO_DEVICE);
0358 err_map_in:
0359 err_alloc:
0360     free_page((unsigned long)dd->buf_out);
0361     free_page((unsigned long)dd->buf_in);
0362     return err;
0363 }
0364 
0365 static void atmel_tdes_buff_cleanup(struct atmel_tdes_dev *dd)
0366 {
0367     dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
0368              DMA_FROM_DEVICE);
0369     dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen,
0370         DMA_TO_DEVICE);
0371     free_page((unsigned long)dd->buf_out);
0372     free_page((unsigned long)dd->buf_in);
0373 }
0374 
0375 static int atmel_tdes_crypt_pdc(struct atmel_tdes_dev *dd,
0376                 dma_addr_t dma_addr_in,
0377                 dma_addr_t dma_addr_out, int length)
0378 {
0379     struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(dd->req);
0380     int len32;
0381 
0382     dd->dma_size = length;
0383 
0384     if (!(dd->flags & TDES_FLAGS_FAST)) {
0385         dma_sync_single_for_device(dd->dev, dma_addr_in, length,
0386                        DMA_TO_DEVICE);
0387     }
0388 
0389     switch (rctx->mode & TDES_FLAGS_OPMODE_MASK) {
0390     case TDES_FLAGS_CFB8:
0391         len32 = DIV_ROUND_UP(length, sizeof(u8));
0392         break;
0393 
0394     case TDES_FLAGS_CFB16:
0395         len32 = DIV_ROUND_UP(length, sizeof(u16));
0396         break;
0397 
0398     default:
0399         len32 = DIV_ROUND_UP(length, sizeof(u32));
0400         break;
0401     }
0402 
0403     atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS);
0404     atmel_tdes_write(dd, TDES_TPR, dma_addr_in);
0405     atmel_tdes_write(dd, TDES_TCR, len32);
0406     atmel_tdes_write(dd, TDES_RPR, dma_addr_out);
0407     atmel_tdes_write(dd, TDES_RCR, len32);
0408 
0409     /* Enable Interrupt */
0410     atmel_tdes_write(dd, TDES_IER, TDES_INT_ENDRX);
0411 
0412     /* Start DMA transfer */
0413     atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTEN | TDES_PTCR_RXTEN);
0414 
0415     return 0;
0416 }
0417 
0418 static int atmel_tdes_crypt_dma(struct atmel_tdes_dev *dd,
0419                 dma_addr_t dma_addr_in,
0420                 dma_addr_t dma_addr_out, int length)
0421 {
0422     struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(dd->req);
0423     struct scatterlist sg[2];
0424     struct dma_async_tx_descriptor  *in_desc, *out_desc;
0425     enum dma_slave_buswidth addr_width;
0426 
0427     dd->dma_size = length;
0428 
0429     if (!(dd->flags & TDES_FLAGS_FAST)) {
0430         dma_sync_single_for_device(dd->dev, dma_addr_in, length,
0431                        DMA_TO_DEVICE);
0432     }
0433 
0434     switch (rctx->mode & TDES_FLAGS_OPMODE_MASK) {
0435     case TDES_FLAGS_CFB8:
0436         addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
0437         break;
0438 
0439     case TDES_FLAGS_CFB16:
0440         addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
0441         break;
0442 
0443     default:
0444         addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0445         break;
0446     }
0447 
0448     dd->dma_lch_in.dma_conf.dst_addr_width = addr_width;
0449     dd->dma_lch_out.dma_conf.src_addr_width = addr_width;
0450 
0451     dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf);
0452     dmaengine_slave_config(dd->dma_lch_out.chan, &dd->dma_lch_out.dma_conf);
0453 
0454     dd->flags |= TDES_FLAGS_DMA;
0455 
0456     sg_init_table(&sg[0], 1);
0457     sg_dma_address(&sg[0]) = dma_addr_in;
0458     sg_dma_len(&sg[0]) = length;
0459 
0460     sg_init_table(&sg[1], 1);
0461     sg_dma_address(&sg[1]) = dma_addr_out;
0462     sg_dma_len(&sg[1]) = length;
0463 
0464     in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, &sg[0],
0465                 1, DMA_MEM_TO_DEV,
0466                 DMA_PREP_INTERRUPT  |  DMA_CTRL_ACK);
0467     if (!in_desc)
0468         return -EINVAL;
0469 
0470     out_desc = dmaengine_prep_slave_sg(dd->dma_lch_out.chan, &sg[1],
0471                 1, DMA_DEV_TO_MEM,
0472                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0473     if (!out_desc)
0474         return -EINVAL;
0475 
0476     out_desc->callback = atmel_tdes_dma_callback;
0477     out_desc->callback_param = dd;
0478 
0479     dmaengine_submit(out_desc);
0480     dma_async_issue_pending(dd->dma_lch_out.chan);
0481 
0482     dmaengine_submit(in_desc);
0483     dma_async_issue_pending(dd->dma_lch_in.chan);
0484 
0485     return 0;
0486 }
0487 
0488 static int atmel_tdes_crypt_start(struct atmel_tdes_dev *dd)
0489 {
0490     int err, fast = 0, in, out;
0491     size_t count;
0492     dma_addr_t addr_in, addr_out;
0493 
0494     if ((!dd->in_offset) && (!dd->out_offset)) {
0495         /* check for alignment */
0496         in = IS_ALIGNED((u32)dd->in_sg->offset, sizeof(u32)) &&
0497             IS_ALIGNED(dd->in_sg->length, dd->ctx->block_size);
0498         out = IS_ALIGNED((u32)dd->out_sg->offset, sizeof(u32)) &&
0499             IS_ALIGNED(dd->out_sg->length, dd->ctx->block_size);
0500         fast = in && out;
0501 
0502         if (sg_dma_len(dd->in_sg) != sg_dma_len(dd->out_sg))
0503             fast = 0;
0504     }
0505 
0506 
0507     if (fast)  {
0508         count = min_t(size_t, dd->total, sg_dma_len(dd->in_sg));
0509         count = min_t(size_t, count, sg_dma_len(dd->out_sg));
0510 
0511         err = dma_map_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
0512         if (!err) {
0513             dev_dbg(dd->dev, "dma_map_sg() error\n");
0514             return -EINVAL;
0515         }
0516 
0517         err = dma_map_sg(dd->dev, dd->out_sg, 1,
0518                 DMA_FROM_DEVICE);
0519         if (!err) {
0520             dev_dbg(dd->dev, "dma_map_sg() error\n");
0521             dma_unmap_sg(dd->dev, dd->in_sg, 1,
0522                 DMA_TO_DEVICE);
0523             return -EINVAL;
0524         }
0525 
0526         addr_in = sg_dma_address(dd->in_sg);
0527         addr_out = sg_dma_address(dd->out_sg);
0528 
0529         dd->flags |= TDES_FLAGS_FAST;
0530 
0531     } else {
0532         /* use cache buffers */
0533         count = atmel_tdes_sg_copy(&dd->in_sg, &dd->in_offset,
0534                 dd->buf_in, dd->buflen, dd->total, 0);
0535 
0536         addr_in = dd->dma_addr_in;
0537         addr_out = dd->dma_addr_out;
0538 
0539         dd->flags &= ~TDES_FLAGS_FAST;
0540     }
0541 
0542     dd->total -= count;
0543 
0544     if (dd->caps.has_dma)
0545         err = atmel_tdes_crypt_dma(dd, addr_in, addr_out, count);
0546     else
0547         err = atmel_tdes_crypt_pdc(dd, addr_in, addr_out, count);
0548 
0549     if (err && (dd->flags & TDES_FLAGS_FAST)) {
0550         dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
0551         dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_TO_DEVICE);
0552     }
0553 
0554     return err;
0555 }
0556 
0557 static void
0558 atmel_tdes_set_iv_as_last_ciphertext_block(struct atmel_tdes_dev *dd)
0559 {
0560     struct skcipher_request *req = dd->req;
0561     struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(req);
0562     struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
0563     unsigned int ivsize = crypto_skcipher_ivsize(skcipher);
0564 
0565     if (req->cryptlen < ivsize)
0566         return;
0567 
0568     if (rctx->mode & TDES_FLAGS_ENCRYPT) {
0569         scatterwalk_map_and_copy(req->iv, req->dst,
0570                      req->cryptlen - ivsize, ivsize, 0);
0571     } else {
0572         if (req->src == req->dst)
0573             memcpy(req->iv, rctx->lastc, ivsize);
0574         else
0575             scatterwalk_map_and_copy(req->iv, req->src,
0576                          req->cryptlen - ivsize,
0577                          ivsize, 0);
0578     }
0579 }
0580 
0581 static void atmel_tdes_finish_req(struct atmel_tdes_dev *dd, int err)
0582 {
0583     struct skcipher_request *req = dd->req;
0584     struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(req);
0585 
0586     clk_disable_unprepare(dd->iclk);
0587 
0588     dd->flags &= ~TDES_FLAGS_BUSY;
0589 
0590     if (!err && (rctx->mode & TDES_FLAGS_OPMODE_MASK) != TDES_FLAGS_ECB)
0591         atmel_tdes_set_iv_as_last_ciphertext_block(dd);
0592 
0593     req->base.complete(&req->base, err);
0594 }
0595 
0596 static int atmel_tdes_handle_queue(struct atmel_tdes_dev *dd,
0597                    struct skcipher_request *req)
0598 {
0599     struct crypto_async_request *async_req, *backlog;
0600     struct atmel_tdes_ctx *ctx;
0601     struct atmel_tdes_reqctx *rctx;
0602     unsigned long flags;
0603     int err, ret = 0;
0604 
0605     spin_lock_irqsave(&dd->lock, flags);
0606     if (req)
0607         ret = crypto_enqueue_request(&dd->queue, &req->base);
0608     if (dd->flags & TDES_FLAGS_BUSY) {
0609         spin_unlock_irqrestore(&dd->lock, flags);
0610         return ret;
0611     }
0612     backlog = crypto_get_backlog(&dd->queue);
0613     async_req = crypto_dequeue_request(&dd->queue);
0614     if (async_req)
0615         dd->flags |= TDES_FLAGS_BUSY;
0616     spin_unlock_irqrestore(&dd->lock, flags);
0617 
0618     if (!async_req)
0619         return ret;
0620 
0621     if (backlog)
0622         backlog->complete(backlog, -EINPROGRESS);
0623 
0624     req = skcipher_request_cast(async_req);
0625 
0626     /* assign new request to device */
0627     dd->req = req;
0628     dd->total = req->cryptlen;
0629     dd->in_offset = 0;
0630     dd->in_sg = req->src;
0631     dd->out_offset = 0;
0632     dd->out_sg = req->dst;
0633 
0634     rctx = skcipher_request_ctx(req);
0635     ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
0636     rctx->mode &= TDES_FLAGS_MODE_MASK;
0637     dd->flags = (dd->flags & ~TDES_FLAGS_MODE_MASK) | rctx->mode;
0638     dd->ctx = ctx;
0639 
0640     err = atmel_tdes_write_ctrl(dd);
0641     if (!err)
0642         err = atmel_tdes_crypt_start(dd);
0643     if (err) {
0644         /* des_task will not finish it, so do it here */
0645         atmel_tdes_finish_req(dd, err);
0646         tasklet_schedule(&dd->queue_task);
0647     }
0648 
0649     return ret;
0650 }
0651 
0652 static int atmel_tdes_crypt_dma_stop(struct atmel_tdes_dev *dd)
0653 {
0654     int err = -EINVAL;
0655     size_t count;
0656 
0657     if (dd->flags & TDES_FLAGS_DMA) {
0658         err = 0;
0659         if  (dd->flags & TDES_FLAGS_FAST) {
0660             dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
0661             dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
0662         } else {
0663             dma_sync_single_for_device(dd->dev, dd->dma_addr_out,
0664                 dd->dma_size, DMA_FROM_DEVICE);
0665 
0666             /* copy data */
0667             count = atmel_tdes_sg_copy(&dd->out_sg, &dd->out_offset,
0668                 dd->buf_out, dd->buflen, dd->dma_size, 1);
0669             if (count != dd->dma_size) {
0670                 err = -EINVAL;
0671                 dev_dbg(dd->dev, "not all data converted: %zu\n", count);
0672             }
0673         }
0674     }
0675     return err;
0676 }
0677 
0678 static int atmel_tdes_crypt(struct skcipher_request *req, unsigned long mode)
0679 {
0680     struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
0681     struct atmel_tdes_ctx *ctx = crypto_skcipher_ctx(skcipher);
0682     struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(req);
0683     struct device *dev = ctx->dd->dev;
0684 
0685     if (!req->cryptlen)
0686         return 0;
0687 
0688     switch (mode & TDES_FLAGS_OPMODE_MASK) {
0689     case TDES_FLAGS_CFB8:
0690         if (!IS_ALIGNED(req->cryptlen, CFB8_BLOCK_SIZE)) {
0691             dev_dbg(dev, "request size is not exact amount of CFB8 blocks\n");
0692             return -EINVAL;
0693         }
0694         ctx->block_size = CFB8_BLOCK_SIZE;
0695         break;
0696 
0697     case TDES_FLAGS_CFB16:
0698         if (!IS_ALIGNED(req->cryptlen, CFB16_BLOCK_SIZE)) {
0699             dev_dbg(dev, "request size is not exact amount of CFB16 blocks\n");
0700             return -EINVAL;
0701         }
0702         ctx->block_size = CFB16_BLOCK_SIZE;
0703         break;
0704 
0705     case TDES_FLAGS_CFB32:
0706         if (!IS_ALIGNED(req->cryptlen, CFB32_BLOCK_SIZE)) {
0707             dev_dbg(dev, "request size is not exact amount of CFB32 blocks\n");
0708             return -EINVAL;
0709         }
0710         ctx->block_size = CFB32_BLOCK_SIZE;
0711         break;
0712 
0713     default:
0714         if (!IS_ALIGNED(req->cryptlen, DES_BLOCK_SIZE)) {
0715             dev_dbg(dev, "request size is not exact amount of DES blocks\n");
0716             return -EINVAL;
0717         }
0718         ctx->block_size = DES_BLOCK_SIZE;
0719         break;
0720     }
0721 
0722     rctx->mode = mode;
0723 
0724     if ((mode & TDES_FLAGS_OPMODE_MASK) != TDES_FLAGS_ECB &&
0725         !(mode & TDES_FLAGS_ENCRYPT) && req->src == req->dst) {
0726         unsigned int ivsize = crypto_skcipher_ivsize(skcipher);
0727 
0728         if (req->cryptlen >= ivsize)
0729             scatterwalk_map_and_copy(rctx->lastc, req->src,
0730                          req->cryptlen - ivsize,
0731                          ivsize, 0);
0732     }
0733 
0734     return atmel_tdes_handle_queue(ctx->dd, req);
0735 }
0736 
0737 static int atmel_tdes_dma_init(struct atmel_tdes_dev *dd)
0738 {
0739     int ret;
0740 
0741     /* Try to grab 2 DMA channels */
0742     dd->dma_lch_in.chan = dma_request_chan(dd->dev, "tx");
0743     if (IS_ERR(dd->dma_lch_in.chan)) {
0744         ret = PTR_ERR(dd->dma_lch_in.chan);
0745         goto err_dma_in;
0746     }
0747 
0748     dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
0749         TDES_IDATA1R;
0750     dd->dma_lch_in.dma_conf.src_maxburst = 1;
0751     dd->dma_lch_in.dma_conf.src_addr_width =
0752         DMA_SLAVE_BUSWIDTH_4_BYTES;
0753     dd->dma_lch_in.dma_conf.dst_maxburst = 1;
0754     dd->dma_lch_in.dma_conf.dst_addr_width =
0755         DMA_SLAVE_BUSWIDTH_4_BYTES;
0756     dd->dma_lch_in.dma_conf.device_fc = false;
0757 
0758     dd->dma_lch_out.chan = dma_request_chan(dd->dev, "rx");
0759     if (IS_ERR(dd->dma_lch_out.chan)) {
0760         ret = PTR_ERR(dd->dma_lch_out.chan);
0761         goto err_dma_out;
0762     }
0763 
0764     dd->dma_lch_out.dma_conf.src_addr = dd->phys_base +
0765         TDES_ODATA1R;
0766     dd->dma_lch_out.dma_conf.src_maxburst = 1;
0767     dd->dma_lch_out.dma_conf.src_addr_width =
0768         DMA_SLAVE_BUSWIDTH_4_BYTES;
0769     dd->dma_lch_out.dma_conf.dst_maxburst = 1;
0770     dd->dma_lch_out.dma_conf.dst_addr_width =
0771         DMA_SLAVE_BUSWIDTH_4_BYTES;
0772     dd->dma_lch_out.dma_conf.device_fc = false;
0773 
0774     return 0;
0775 
0776 err_dma_out:
0777     dma_release_channel(dd->dma_lch_in.chan);
0778 err_dma_in:
0779     dev_err(dd->dev, "no DMA channel available\n");
0780     return ret;
0781 }
0782 
0783 static void atmel_tdes_dma_cleanup(struct atmel_tdes_dev *dd)
0784 {
0785     dma_release_channel(dd->dma_lch_in.chan);
0786     dma_release_channel(dd->dma_lch_out.chan);
0787 }
0788 
0789 static int atmel_des_setkey(struct crypto_skcipher *tfm, const u8 *key,
0790                unsigned int keylen)
0791 {
0792     struct atmel_tdes_ctx *ctx = crypto_skcipher_ctx(tfm);
0793     int err;
0794 
0795     err = verify_skcipher_des_key(tfm, key);
0796     if (err)
0797         return err;
0798 
0799     memcpy(ctx->key, key, keylen);
0800     ctx->keylen = keylen;
0801 
0802     return 0;
0803 }
0804 
0805 static int atmel_tdes_setkey(struct crypto_skcipher *tfm, const u8 *key,
0806                unsigned int keylen)
0807 {
0808     struct atmel_tdes_ctx *ctx = crypto_skcipher_ctx(tfm);
0809     int err;
0810 
0811     err = verify_skcipher_des3_key(tfm, key);
0812     if (err)
0813         return err;
0814 
0815     memcpy(ctx->key, key, keylen);
0816     ctx->keylen = keylen;
0817 
0818     return 0;
0819 }
0820 
0821 static int atmel_tdes_ecb_encrypt(struct skcipher_request *req)
0822 {
0823     return atmel_tdes_crypt(req, TDES_FLAGS_ECB | TDES_FLAGS_ENCRYPT);
0824 }
0825 
0826 static int atmel_tdes_ecb_decrypt(struct skcipher_request *req)
0827 {
0828     return atmel_tdes_crypt(req, TDES_FLAGS_ECB);
0829 }
0830 
0831 static int atmel_tdes_cbc_encrypt(struct skcipher_request *req)
0832 {
0833     return atmel_tdes_crypt(req, TDES_FLAGS_CBC | TDES_FLAGS_ENCRYPT);
0834 }
0835 
0836 static int atmel_tdes_cbc_decrypt(struct skcipher_request *req)
0837 {
0838     return atmel_tdes_crypt(req, TDES_FLAGS_CBC);
0839 }
0840 static int atmel_tdes_cfb_encrypt(struct skcipher_request *req)
0841 {
0842     return atmel_tdes_crypt(req, TDES_FLAGS_CFB64 | TDES_FLAGS_ENCRYPT);
0843 }
0844 
0845 static int atmel_tdes_cfb_decrypt(struct skcipher_request *req)
0846 {
0847     return atmel_tdes_crypt(req, TDES_FLAGS_CFB64);
0848 }
0849 
0850 static int atmel_tdes_cfb8_encrypt(struct skcipher_request *req)
0851 {
0852     return atmel_tdes_crypt(req, TDES_FLAGS_CFB8 | TDES_FLAGS_ENCRYPT);
0853 }
0854 
0855 static int atmel_tdes_cfb8_decrypt(struct skcipher_request *req)
0856 {
0857     return atmel_tdes_crypt(req, TDES_FLAGS_CFB8);
0858 }
0859 
0860 static int atmel_tdes_cfb16_encrypt(struct skcipher_request *req)
0861 {
0862     return atmel_tdes_crypt(req, TDES_FLAGS_CFB16 | TDES_FLAGS_ENCRYPT);
0863 }
0864 
0865 static int atmel_tdes_cfb16_decrypt(struct skcipher_request *req)
0866 {
0867     return atmel_tdes_crypt(req, TDES_FLAGS_CFB16);
0868 }
0869 
0870 static int atmel_tdes_cfb32_encrypt(struct skcipher_request *req)
0871 {
0872     return atmel_tdes_crypt(req, TDES_FLAGS_CFB32 | TDES_FLAGS_ENCRYPT);
0873 }
0874 
0875 static int atmel_tdes_cfb32_decrypt(struct skcipher_request *req)
0876 {
0877     return atmel_tdes_crypt(req, TDES_FLAGS_CFB32);
0878 }
0879 
0880 static int atmel_tdes_ofb_encrypt(struct skcipher_request *req)
0881 {
0882     return atmel_tdes_crypt(req, TDES_FLAGS_OFB | TDES_FLAGS_ENCRYPT);
0883 }
0884 
0885 static int atmel_tdes_ofb_decrypt(struct skcipher_request *req)
0886 {
0887     return atmel_tdes_crypt(req, TDES_FLAGS_OFB);
0888 }
0889 
0890 static int atmel_tdes_init_tfm(struct crypto_skcipher *tfm)
0891 {
0892     struct atmel_tdes_ctx *ctx = crypto_skcipher_ctx(tfm);
0893 
0894     ctx->dd = atmel_tdes_dev_alloc();
0895     if (!ctx->dd)
0896         return -ENODEV;
0897 
0898     crypto_skcipher_set_reqsize(tfm, sizeof(struct atmel_tdes_reqctx));
0899 
0900     return 0;
0901 }
0902 
0903 static void atmel_tdes_skcipher_alg_init(struct skcipher_alg *alg)
0904 {
0905     alg->base.cra_priority = ATMEL_TDES_PRIORITY;
0906     alg->base.cra_flags = CRYPTO_ALG_ASYNC;
0907     alg->base.cra_ctxsize = sizeof(struct atmel_tdes_ctx);
0908     alg->base.cra_module = THIS_MODULE;
0909 
0910     alg->init = atmel_tdes_init_tfm;
0911 }
0912 
0913 static struct skcipher_alg tdes_algs[] = {
0914 {
0915     .base.cra_name      = "ecb(des)",
0916     .base.cra_driver_name   = "atmel-ecb-des",
0917     .base.cra_blocksize = DES_BLOCK_SIZE,
0918     .base.cra_alignmask = 0x7,
0919 
0920     .min_keysize        = DES_KEY_SIZE,
0921     .max_keysize        = DES_KEY_SIZE,
0922     .setkey         = atmel_des_setkey,
0923     .encrypt        = atmel_tdes_ecb_encrypt,
0924     .decrypt        = atmel_tdes_ecb_decrypt,
0925 },
0926 {
0927     .base.cra_name      = "cbc(des)",
0928     .base.cra_driver_name   = "atmel-cbc-des",
0929     .base.cra_blocksize = DES_BLOCK_SIZE,
0930     .base.cra_alignmask = 0x7,
0931 
0932     .min_keysize        = DES_KEY_SIZE,
0933     .max_keysize        = DES_KEY_SIZE,
0934     .ivsize         = DES_BLOCK_SIZE,
0935     .setkey         = atmel_des_setkey,
0936     .encrypt        = atmel_tdes_cbc_encrypt,
0937     .decrypt        = atmel_tdes_cbc_decrypt,
0938 },
0939 {
0940     .base.cra_name      = "cfb(des)",
0941     .base.cra_driver_name   = "atmel-cfb-des",
0942     .base.cra_blocksize = DES_BLOCK_SIZE,
0943     .base.cra_alignmask = 0x7,
0944 
0945     .min_keysize        = DES_KEY_SIZE,
0946     .max_keysize        = DES_KEY_SIZE,
0947     .ivsize         = DES_BLOCK_SIZE,
0948     .setkey         = atmel_des_setkey,
0949     .encrypt        = atmel_tdes_cfb_encrypt,
0950     .decrypt        = atmel_tdes_cfb_decrypt,
0951 },
0952 {
0953     .base.cra_name      = "cfb8(des)",
0954     .base.cra_driver_name   = "atmel-cfb8-des",
0955     .base.cra_blocksize = CFB8_BLOCK_SIZE,
0956     .base.cra_alignmask = 0,
0957 
0958     .min_keysize        = DES_KEY_SIZE,
0959     .max_keysize        = DES_KEY_SIZE,
0960     .ivsize         = DES_BLOCK_SIZE,
0961     .setkey         = atmel_des_setkey,
0962     .encrypt        = atmel_tdes_cfb8_encrypt,
0963     .decrypt        = atmel_tdes_cfb8_decrypt,
0964 },
0965 {
0966     .base.cra_name      = "cfb16(des)",
0967     .base.cra_driver_name   = "atmel-cfb16-des",
0968     .base.cra_blocksize = CFB16_BLOCK_SIZE,
0969     .base.cra_alignmask = 0x1,
0970 
0971     .min_keysize        = DES_KEY_SIZE,
0972     .max_keysize        = DES_KEY_SIZE,
0973     .ivsize         = DES_BLOCK_SIZE,
0974     .setkey         = atmel_des_setkey,
0975     .encrypt        = atmel_tdes_cfb16_encrypt,
0976     .decrypt        = atmel_tdes_cfb16_decrypt,
0977 },
0978 {
0979     .base.cra_name      = "cfb32(des)",
0980     .base.cra_driver_name   = "atmel-cfb32-des",
0981     .base.cra_blocksize = CFB32_BLOCK_SIZE,
0982     .base.cra_alignmask = 0x3,
0983 
0984     .min_keysize        = DES_KEY_SIZE,
0985     .max_keysize        = DES_KEY_SIZE,
0986     .ivsize         = DES_BLOCK_SIZE,
0987     .setkey         = atmel_des_setkey,
0988     .encrypt        = atmel_tdes_cfb32_encrypt,
0989     .decrypt        = atmel_tdes_cfb32_decrypt,
0990 },
0991 {
0992     .base.cra_name      = "ofb(des)",
0993     .base.cra_driver_name   = "atmel-ofb-des",
0994     .base.cra_blocksize = 1,
0995     .base.cra_alignmask = 0x7,
0996 
0997     .min_keysize        = DES_KEY_SIZE,
0998     .max_keysize        = DES_KEY_SIZE,
0999     .ivsize         = DES_BLOCK_SIZE,
1000     .setkey         = atmel_des_setkey,
1001     .encrypt        = atmel_tdes_ofb_encrypt,
1002     .decrypt        = atmel_tdes_ofb_decrypt,
1003 },
1004 {
1005     .base.cra_name      = "ecb(des3_ede)",
1006     .base.cra_driver_name   = "atmel-ecb-tdes",
1007     .base.cra_blocksize = DES_BLOCK_SIZE,
1008     .base.cra_alignmask = 0x7,
1009 
1010     .min_keysize        = DES3_EDE_KEY_SIZE,
1011     .max_keysize        = DES3_EDE_KEY_SIZE,
1012     .setkey         = atmel_tdes_setkey,
1013     .encrypt        = atmel_tdes_ecb_encrypt,
1014     .decrypt        = atmel_tdes_ecb_decrypt,
1015 },
1016 {
1017     .base.cra_name      = "cbc(des3_ede)",
1018     .base.cra_driver_name   = "atmel-cbc-tdes",
1019     .base.cra_blocksize = DES_BLOCK_SIZE,
1020     .base.cra_alignmask = 0x7,
1021 
1022     .min_keysize        = DES3_EDE_KEY_SIZE,
1023     .max_keysize        = DES3_EDE_KEY_SIZE,
1024     .setkey         = atmel_tdes_setkey,
1025     .encrypt        = atmel_tdes_cbc_encrypt,
1026     .decrypt        = atmel_tdes_cbc_decrypt,
1027     .ivsize         = DES_BLOCK_SIZE,
1028 },
1029 {
1030     .base.cra_name      = "ofb(des3_ede)",
1031     .base.cra_driver_name   = "atmel-ofb-tdes",
1032     .base.cra_blocksize = DES_BLOCK_SIZE,
1033     .base.cra_alignmask = 0x7,
1034 
1035     .min_keysize        = DES3_EDE_KEY_SIZE,
1036     .max_keysize        = DES3_EDE_KEY_SIZE,
1037     .setkey         = atmel_tdes_setkey,
1038     .encrypt        = atmel_tdes_ofb_encrypt,
1039     .decrypt        = atmel_tdes_ofb_decrypt,
1040     .ivsize         = DES_BLOCK_SIZE,
1041 },
1042 };
1043 
1044 static void atmel_tdes_queue_task(unsigned long data)
1045 {
1046     struct atmel_tdes_dev *dd = (struct atmel_tdes_dev *)data;
1047 
1048     atmel_tdes_handle_queue(dd, NULL);
1049 }
1050 
1051 static void atmel_tdes_done_task(unsigned long data)
1052 {
1053     struct atmel_tdes_dev *dd = (struct atmel_tdes_dev *) data;
1054     int err;
1055 
1056     if (!(dd->flags & TDES_FLAGS_DMA))
1057         err = atmel_tdes_crypt_pdc_stop(dd);
1058     else
1059         err = atmel_tdes_crypt_dma_stop(dd);
1060 
1061     if (dd->total && !err) {
1062         if (dd->flags & TDES_FLAGS_FAST) {
1063             dd->in_sg = sg_next(dd->in_sg);
1064             dd->out_sg = sg_next(dd->out_sg);
1065             if (!dd->in_sg || !dd->out_sg)
1066                 err = -EINVAL;
1067         }
1068         if (!err)
1069             err = atmel_tdes_crypt_start(dd);
1070         if (!err)
1071             return; /* DMA started. Not fininishing. */
1072     }
1073 
1074     atmel_tdes_finish_req(dd, err);
1075     atmel_tdes_handle_queue(dd, NULL);
1076 }
1077 
1078 static irqreturn_t atmel_tdes_irq(int irq, void *dev_id)
1079 {
1080     struct atmel_tdes_dev *tdes_dd = dev_id;
1081     u32 reg;
1082 
1083     reg = atmel_tdes_read(tdes_dd, TDES_ISR);
1084     if (reg & atmel_tdes_read(tdes_dd, TDES_IMR)) {
1085         atmel_tdes_write(tdes_dd, TDES_IDR, reg);
1086         if (TDES_FLAGS_BUSY & tdes_dd->flags)
1087             tasklet_schedule(&tdes_dd->done_task);
1088         else
1089             dev_warn(tdes_dd->dev, "TDES interrupt when no active requests.\n");
1090         return IRQ_HANDLED;
1091     }
1092 
1093     return IRQ_NONE;
1094 }
1095 
1096 static void atmel_tdes_unregister_algs(struct atmel_tdes_dev *dd)
1097 {
1098     int i;
1099 
1100     for (i = 0; i < ARRAY_SIZE(tdes_algs); i++)
1101         crypto_unregister_skcipher(&tdes_algs[i]);
1102 }
1103 
1104 static int atmel_tdes_register_algs(struct atmel_tdes_dev *dd)
1105 {
1106     int err, i, j;
1107 
1108     for (i = 0; i < ARRAY_SIZE(tdes_algs); i++) {
1109         atmel_tdes_skcipher_alg_init(&tdes_algs[i]);
1110 
1111         err = crypto_register_skcipher(&tdes_algs[i]);
1112         if (err)
1113             goto err_tdes_algs;
1114     }
1115 
1116     return 0;
1117 
1118 err_tdes_algs:
1119     for (j = 0; j < i; j++)
1120         crypto_unregister_skcipher(&tdes_algs[j]);
1121 
1122     return err;
1123 }
1124 
1125 static void atmel_tdes_get_cap(struct atmel_tdes_dev *dd)
1126 {
1127 
1128     dd->caps.has_dma = 0;
1129     dd->caps.has_cfb_3keys = 0;
1130 
1131     /* keep only major version number */
1132     switch (dd->hw_version & 0xf00) {
1133     case 0x800:
1134     case 0x700:
1135         dd->caps.has_dma = 1;
1136         dd->caps.has_cfb_3keys = 1;
1137         break;
1138     case 0x600:
1139         break;
1140     default:
1141         dev_warn(dd->dev,
1142                 "Unmanaged tdes version, set minimum capabilities\n");
1143         break;
1144     }
1145 }
1146 
1147 #if defined(CONFIG_OF)
1148 static const struct of_device_id atmel_tdes_dt_ids[] = {
1149     { .compatible = "atmel,at91sam9g46-tdes" },
1150     { /* sentinel */ }
1151 };
1152 MODULE_DEVICE_TABLE(of, atmel_tdes_dt_ids);
1153 #endif
1154 
1155 static int atmel_tdes_probe(struct platform_device *pdev)
1156 {
1157     struct atmel_tdes_dev *tdes_dd;
1158     struct device *dev = &pdev->dev;
1159     struct resource *tdes_res;
1160     int err;
1161 
1162     tdes_dd = devm_kmalloc(&pdev->dev, sizeof(*tdes_dd), GFP_KERNEL);
1163     if (!tdes_dd)
1164         return -ENOMEM;
1165 
1166     tdes_dd->dev = dev;
1167 
1168     platform_set_drvdata(pdev, tdes_dd);
1169 
1170     INIT_LIST_HEAD(&tdes_dd->list);
1171     spin_lock_init(&tdes_dd->lock);
1172 
1173     tasklet_init(&tdes_dd->done_task, atmel_tdes_done_task,
1174                     (unsigned long)tdes_dd);
1175     tasklet_init(&tdes_dd->queue_task, atmel_tdes_queue_task,
1176                     (unsigned long)tdes_dd);
1177 
1178     crypto_init_queue(&tdes_dd->queue, ATMEL_TDES_QUEUE_LENGTH);
1179 
1180     /* Get the base address */
1181     tdes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1182     if (!tdes_res) {
1183         dev_err(dev, "no MEM resource info\n");
1184         err = -ENODEV;
1185         goto err_tasklet_kill;
1186     }
1187     tdes_dd->phys_base = tdes_res->start;
1188 
1189     /* Get the IRQ */
1190     tdes_dd->irq = platform_get_irq(pdev,  0);
1191     if (tdes_dd->irq < 0) {
1192         err = tdes_dd->irq;
1193         goto err_tasklet_kill;
1194     }
1195 
1196     err = devm_request_irq(&pdev->dev, tdes_dd->irq, atmel_tdes_irq,
1197                    IRQF_SHARED, "atmel-tdes", tdes_dd);
1198     if (err) {
1199         dev_err(dev, "unable to request tdes irq.\n");
1200         goto err_tasklet_kill;
1201     }
1202 
1203     /* Initializing the clock */
1204     tdes_dd->iclk = devm_clk_get(&pdev->dev, "tdes_clk");
1205     if (IS_ERR(tdes_dd->iclk)) {
1206         dev_err(dev, "clock initialization failed.\n");
1207         err = PTR_ERR(tdes_dd->iclk);
1208         goto err_tasklet_kill;
1209     }
1210 
1211     tdes_dd->io_base = devm_ioremap_resource(&pdev->dev, tdes_res);
1212     if (IS_ERR(tdes_dd->io_base)) {
1213         err = PTR_ERR(tdes_dd->io_base);
1214         goto err_tasklet_kill;
1215     }
1216 
1217     err = atmel_tdes_hw_version_init(tdes_dd);
1218     if (err)
1219         goto err_tasklet_kill;
1220 
1221     atmel_tdes_get_cap(tdes_dd);
1222 
1223     err = atmel_tdes_buff_init(tdes_dd);
1224     if (err)
1225         goto err_tasklet_kill;
1226 
1227     if (tdes_dd->caps.has_dma) {
1228         err = atmel_tdes_dma_init(tdes_dd);
1229         if (err)
1230             goto err_buff_cleanup;
1231 
1232         dev_info(dev, "using %s, %s for DMA transfers\n",
1233                 dma_chan_name(tdes_dd->dma_lch_in.chan),
1234                 dma_chan_name(tdes_dd->dma_lch_out.chan));
1235     }
1236 
1237     spin_lock(&atmel_tdes.lock);
1238     list_add_tail(&tdes_dd->list, &atmel_tdes.dev_list);
1239     spin_unlock(&atmel_tdes.lock);
1240 
1241     err = atmel_tdes_register_algs(tdes_dd);
1242     if (err)
1243         goto err_algs;
1244 
1245     dev_info(dev, "Atmel DES/TDES\n");
1246 
1247     return 0;
1248 
1249 err_algs:
1250     spin_lock(&atmel_tdes.lock);
1251     list_del(&tdes_dd->list);
1252     spin_unlock(&atmel_tdes.lock);
1253     if (tdes_dd->caps.has_dma)
1254         atmel_tdes_dma_cleanup(tdes_dd);
1255 err_buff_cleanup:
1256     atmel_tdes_buff_cleanup(tdes_dd);
1257 err_tasklet_kill:
1258     tasklet_kill(&tdes_dd->done_task);
1259     tasklet_kill(&tdes_dd->queue_task);
1260 
1261     return err;
1262 }
1263 
1264 static int atmel_tdes_remove(struct platform_device *pdev)
1265 {
1266     struct atmel_tdes_dev *tdes_dd = platform_get_drvdata(pdev);
1267 
1268     spin_lock(&atmel_tdes.lock);
1269     list_del(&tdes_dd->list);
1270     spin_unlock(&atmel_tdes.lock);
1271 
1272     atmel_tdes_unregister_algs(tdes_dd);
1273 
1274     tasklet_kill(&tdes_dd->done_task);
1275     tasklet_kill(&tdes_dd->queue_task);
1276 
1277     if (tdes_dd->caps.has_dma)
1278         atmel_tdes_dma_cleanup(tdes_dd);
1279 
1280     atmel_tdes_buff_cleanup(tdes_dd);
1281 
1282     return 0;
1283 }
1284 
1285 static struct platform_driver atmel_tdes_driver = {
1286     .probe      = atmel_tdes_probe,
1287     .remove     = atmel_tdes_remove,
1288     .driver     = {
1289         .name   = "atmel_tdes",
1290         .of_match_table = of_match_ptr(atmel_tdes_dt_ids),
1291     },
1292 };
1293 
1294 module_platform_driver(atmel_tdes_driver);
1295 
1296 MODULE_DESCRIPTION("Atmel DES/TDES hw acceleration support.");
1297 MODULE_LICENSE("GPL v2");
1298 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");
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