drivers/crypto/atmel-aes-regs.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ATMEL_AES_REGS_H__
0003 #define __ATMEL_AES_REGS_H__
0004
0005 #define AES_CR          0x00
0006 #define AES_CR_START        (1 << 0)
0007 #define AES_CR_SWRST        (1 << 8)
0008 #define AES_CR_LOADSEED     (1 << 16)
0009
0010 #define AES_MR          0x04
0011 #define AES_MR_CYPHER_DEC       (0 << 0)
0012 #define AES_MR_CYPHER_ENC       (1 << 0)
0013 #define AES_MR_GTAGEN           (1 << 1)
0014 #define AES_MR_DUALBUFF         (1 << 3)
0015 #define AES_MR_PROCDLY_MASK     (0xF << 4)
0016 #define AES_MR_PROCDLY_OFFSET   4
0017 #define AES_MR_SMOD_MASK        (0x3 << 8)
0018 #define AES_MR_SMOD_MANUAL      (0x0 << 8)
0019 #define AES_MR_SMOD_AUTO        (0x1 << 8)
0020 #define AES_MR_SMOD_IDATAR0     (0x2 << 8)
0021 #define AES_MR_KEYSIZE_MASK     (0x3 << 10)
0022 #define AES_MR_KEYSIZE_128      (0x0 << 10)
0023 #define AES_MR_KEYSIZE_192      (0x1 << 10)
0024 #define AES_MR_KEYSIZE_256      (0x2 << 10)
0025 #define AES_MR_OPMOD_MASK       (0x7 << 12)
0026 #define AES_MR_OPMOD_ECB        (0x0 << 12)
0027 #define AES_MR_OPMOD_CBC        (0x1 << 12)
0028 #define AES_MR_OPMOD_OFB        (0x2 << 12)
0029 #define AES_MR_OPMOD_CFB        (0x3 << 12)
0030 #define AES_MR_OPMOD_CTR        (0x4 << 12)
0031 #define AES_MR_OPMOD_GCM        (0x5 << 12)
0032 #define AES_MR_OPMOD_XTS        (0x6 << 12)
0033 #define AES_MR_LOD              (0x1 << 15)
0034 #define AES_MR_CFBS_MASK        (0x7 << 16)
0035 #define AES_MR_CFBS_128b        (0x0 << 16)
0036 #define AES_MR_CFBS_64b         (0x1 << 16)
0037 #define AES_MR_CFBS_32b         (0x2 << 16)
0038 #define AES_MR_CFBS_16b         (0x3 << 16)
0039 #define AES_MR_CFBS_8b          (0x4 << 16)
0040 #define AES_MR_CKEY_MASK        (0xF << 20)
0041 #define AES_MR_CKEY_OFFSET      20
0042 #define AES_MR_CMTYP_MASK       (0x1F << 24)
0043 #define AES_MR_CMTYP_OFFSET     24
0044
0045 #define AES_IER     0x10
0046 #define AES_IDR     0x14
0047 #define AES_IMR     0x18
0048 #define AES_ISR     0x1C
0049 #define AES_INT_DATARDY     (1 << 0)
0050 #define AES_INT_URAD        (1 << 8)
0051 #define AES_INT_TAGRDY      (1 << 16)
0052 #define AES_ISR_URAT_MASK   (0xF << 12)
0053 #define AES_ISR_URAT_IDR_WR_PROC    (0x0 << 12)
0054 #define AES_ISR_URAT_ODR_RD_PROC    (0x1 << 12)
0055 #define AES_ISR_URAT_MR_WR_PROC     (0x2 << 12)
0056 #define AES_ISR_URAT_ODR_RD_SUBK    (0x3 << 12)
0057 #define AES_ISR_URAT_MR_WR_SUBK     (0x4 << 12)
0058 #define AES_ISR_URAT_WOR_RD         (0x5 << 12)
0059
0060 #define AES_KEYWR(x)    (0x20 + ((x) * 0x04))
0061 #define AES_IDATAR(x)   (0x40 + ((x) * 0x04))
0062 #define AES_ODATAR(x)   (0x50 + ((x) * 0x04))
0063 #define AES_IVR(x)      (0x60 + ((x) * 0x04))
0064
0065 #define AES_AADLENR 0x70
0066 #define AES_CLENR   0x74
0067 #define AES_GHASHR(x)   (0x78 + ((x) * 0x04))
0068 #define AES_TAGR(x) (0x88 + ((x) * 0x04))
0069 #define AES_CTRR    0x98
0070 #define AES_GCMHR(x)    (0x9c + ((x) * 0x04))
0071
0072 #define AES_EMR     0xb0
0073 #define AES_EMR_APEN        BIT(0)  /* Auto Padding Enable */
0074 #define AES_EMR_APM     BIT(1)  /* Auto Padding Mode */
0075 #define AES_EMR_APM_IPSEC   0x0
0076 #define AES_EMR_APM_SSL     BIT(1)
0077 #define AES_EMR_PLIPEN      BIT(4)  /* PLIP Enable */
0078 #define AES_EMR_PLIPD       BIT(5)  /* PLIP Decipher */
0079 #define AES_EMR_PADLEN_MASK (0xFu << 8)
0080 #define AES_EMR_PADLEN_OFFSET   8
0081 #define AES_EMR_PADLEN(padlen)  (((padlen) << AES_EMR_PADLEN_OFFSET) &\
0082                  AES_EMR_PADLEN_MASK)
0083 #define AES_EMR_NHEAD_MASK  (0xFu << 16)
0084 #define AES_EMR_NHEAD_OFFSET    16
0085 #define AES_EMR_NHEAD(nhead)    (((nhead) << AES_EMR_NHEAD_OFFSET) &\
0086                  AES_EMR_NHEAD_MASK)
0087
0088 #define AES_TWR(x)  (0xc0 + ((x) * 0x04))
0089 #define AES_ALPHAR(x)   (0xd0 + ((x) * 0x04))
0090
0091 #define AES_HW_VERSION  0xFC
0092
0093 #endif /* __ATMEL_AES_REGS_H__ */