drivers/cpuidle/cpuidle-zynq.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2012-2013 Xilinx
0004  *
0005  * CPU idle support for Xilinx Zynq
0006  *
0007  * based on arch/arm/mach-at91/cpuidle.c
0008  *
0009  * The cpu idle uses wait-for-interrupt and RAM self refresh in order
0010  * to implement two idle states -
0011  * #1 wait-for-interrupt
0012  * #2 wait-for-interrupt and RAM self refresh
0013  *
0014  * Maintainer: Michal Simek <michal.simek@xilinx.com>
0015  */
0016
0017 #include <linux/init.h>
0018 #include <linux/cpuidle.h>
0019 #include <linux/platform_device.h>
0020 #include <asm/cpuidle.h>
0021
0022 #define ZYNQ_MAX_STATES     2
0023
0024 /* Actual code that puts the SoC in different idle states */
0025 static int zynq_enter_idle(struct cpuidle_device *dev,
0026                struct cpuidle_driver *drv, int index)
0027 {
0028     /* Add code for DDR self refresh start */
0029     cpu_do_idle();
0030
0031     return index;
0032 }
0033
0034 static struct cpuidle_driver zynq_idle_driver = {
0035     .name = "zynq_idle",
0036     .owner = THIS_MODULE,
0037     .states = {
0038         ARM_CPUIDLE_WFI_STATE,
0039         {
0040             .enter          = zynq_enter_idle,
0041             .exit_latency       = 10,
0042             .target_residency   = 10000,
0043             .name           = "RAM_SR",
0044             .desc           = "WFI and RAM Self Refresh",
0045         },
0046     },
0047     .safe_state_index = 0,
0048     .state_count = ZYNQ_MAX_STATES,
0049 };
0050
0051 /* Initialize CPU idle by registering the idle states */
0052 static int zynq_cpuidle_probe(struct platform_device *pdev)
0053 {
0054     pr_info("Xilinx Zynq CpuIdle Driver started\n");
0055
0056     return cpuidle_register(&zynq_idle_driver, NULL);
0057 }
0058
0059 static struct platform_driver zynq_cpuidle_driver = {
0060     .driver = {
0061         .name = "cpuidle-zynq",
0062     },
0063     .probe = zynq_cpuidle_probe,
0064 };
0065 builtin_platform_driver(zynq_cpuidle_driver);