Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
0004  * M (part of the Centrino chipset).
0005  *
0006  * Since the original Pentium M, most new Intel CPUs support Enhanced
0007  * SpeedStep.
0008  *
0009  * Despite the "SpeedStep" in the name, this is almost entirely unlike
0010  * traditional SpeedStep.
0011  *
0012  * Modelled on speedstep.c
0013  *
0014  * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
0015  */
0016 
0017 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0018 
0019 #include <linux/kernel.h>
0020 #include <linux/module.h>
0021 #include <linux/init.h>
0022 #include <linux/cpufreq.h>
0023 #include <linux/sched.h>    /* current */
0024 #include <linux/delay.h>
0025 #include <linux/compiler.h>
0026 #include <linux/gfp.h>
0027 
0028 #include <asm/msr.h>
0029 #include <asm/processor.h>
0030 #include <asm/cpufeature.h>
0031 #include <asm/cpu_device_id.h>
0032 
0033 #define MAINTAINER  "linux-pm@vger.kernel.org"
0034 
0035 #define INTEL_MSR_RANGE (0xffff)
0036 
0037 struct cpu_id
0038 {
0039     __u8    x86;            /* CPU family */
0040     __u8    x86_model;  /* model */
0041     __u8    x86_stepping;   /* stepping */
0042 };
0043 
0044 enum {
0045     CPU_BANIAS,
0046     CPU_DOTHAN_A1,
0047     CPU_DOTHAN_A2,
0048     CPU_DOTHAN_B0,
0049     CPU_MP4HT_D0,
0050     CPU_MP4HT_E0,
0051 };
0052 
0053 static const struct cpu_id cpu_ids[] = {
0054     [CPU_BANIAS]    = { 6,  9, 5 },
0055     [CPU_DOTHAN_A1] = { 6, 13, 1 },
0056     [CPU_DOTHAN_A2] = { 6, 13, 2 },
0057     [CPU_DOTHAN_B0] = { 6, 13, 6 },
0058     [CPU_MP4HT_D0]  = {15,  3, 4 },
0059     [CPU_MP4HT_E0]  = {15,  4, 1 },
0060 };
0061 #define N_IDS   ARRAY_SIZE(cpu_ids)
0062 
0063 struct cpu_model
0064 {
0065     const struct cpu_id *cpu_id;
0066     const char  *model_name;
0067     unsigned    max_freq; /* max clock in kHz */
0068 
0069     struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
0070 };
0071 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
0072                   const struct cpu_id *x);
0073 
0074 /* Operating points for current CPU */
0075 static DEFINE_PER_CPU(struct cpu_model *, centrino_model);
0076 static DEFINE_PER_CPU(const struct cpu_id *, centrino_cpu);
0077 
0078 static struct cpufreq_driver centrino_driver;
0079 
0080 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
0081 
0082 /* Computes the correct form for IA32_PERF_CTL MSR for a particular
0083    frequency/voltage operating point; frequency in MHz, volts in mV.
0084    This is stored as "driver_data" in the structure. */
0085 #define OP(mhz, mv)                         \
0086     {                               \
0087         .frequency = (mhz) * 1000,              \
0088         .driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16)       \
0089     }
0090 
0091 /*
0092  * These voltage tables were derived from the Intel Pentium M
0093  * datasheet, document 25261202.pdf, Table 5.  I have verified they
0094  * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
0095  * M.
0096  */
0097 
0098 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
0099 static struct cpufreq_frequency_table banias_900[] =
0100 {
0101     OP(600,  844),
0102     OP(800,  988),
0103     OP(900, 1004),
0104     { .frequency = CPUFREQ_TABLE_END }
0105 };
0106 
0107 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
0108 static struct cpufreq_frequency_table banias_1000[] =
0109 {
0110     OP(600,   844),
0111     OP(800,   972),
0112     OP(900,   988),
0113     OP(1000, 1004),
0114     { .frequency = CPUFREQ_TABLE_END }
0115 };
0116 
0117 /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
0118 static struct cpufreq_frequency_table banias_1100[] =
0119 {
0120     OP( 600,  956),
0121     OP( 800, 1020),
0122     OP( 900, 1100),
0123     OP(1000, 1164),
0124     OP(1100, 1180),
0125     { .frequency = CPUFREQ_TABLE_END }
0126 };
0127 
0128 
0129 /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
0130 static struct cpufreq_frequency_table banias_1200[] =
0131 {
0132     OP( 600,  956),
0133     OP( 800, 1004),
0134     OP( 900, 1020),
0135     OP(1000, 1100),
0136     OP(1100, 1164),
0137     OP(1200, 1180),
0138     { .frequency = CPUFREQ_TABLE_END }
0139 };
0140 
0141 /* Intel Pentium M processor 1.30GHz (Banias) */
0142 static struct cpufreq_frequency_table banias_1300[] =
0143 {
0144     OP( 600,  956),
0145     OP( 800, 1260),
0146     OP(1000, 1292),
0147     OP(1200, 1356),
0148     OP(1300, 1388),
0149     { .frequency = CPUFREQ_TABLE_END }
0150 };
0151 
0152 /* Intel Pentium M processor 1.40GHz (Banias) */
0153 static struct cpufreq_frequency_table banias_1400[] =
0154 {
0155     OP( 600,  956),
0156     OP( 800, 1180),
0157     OP(1000, 1308),
0158     OP(1200, 1436),
0159     OP(1400, 1484),
0160     { .frequency = CPUFREQ_TABLE_END }
0161 };
0162 
0163 /* Intel Pentium M processor 1.50GHz (Banias) */
0164 static struct cpufreq_frequency_table banias_1500[] =
0165 {
0166     OP( 600,  956),
0167     OP( 800, 1116),
0168     OP(1000, 1228),
0169     OP(1200, 1356),
0170     OP(1400, 1452),
0171     OP(1500, 1484),
0172     { .frequency = CPUFREQ_TABLE_END }
0173 };
0174 
0175 /* Intel Pentium M processor 1.60GHz (Banias) */
0176 static struct cpufreq_frequency_table banias_1600[] =
0177 {
0178     OP( 600,  956),
0179     OP( 800, 1036),
0180     OP(1000, 1164),
0181     OP(1200, 1276),
0182     OP(1400, 1420),
0183     OP(1600, 1484),
0184     { .frequency = CPUFREQ_TABLE_END }
0185 };
0186 
0187 /* Intel Pentium M processor 1.70GHz (Banias) */
0188 static struct cpufreq_frequency_table banias_1700[] =
0189 {
0190     OP( 600,  956),
0191     OP( 800, 1004),
0192     OP(1000, 1116),
0193     OP(1200, 1228),
0194     OP(1400, 1308),
0195     OP(1700, 1484),
0196     { .frequency = CPUFREQ_TABLE_END }
0197 };
0198 #undef OP
0199 
0200 #define _BANIAS(cpuid, max, name)   \
0201 {   .cpu_id     = cpuid,    \
0202     .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
0203     .max_freq   = (max)*1000,   \
0204     .op_points  = banias_##max, \
0205 }
0206 #define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
0207 
0208 /* CPU models, their operating frequency range, and freq/voltage
0209    operating points */
0210 static struct cpu_model models[] =
0211 {
0212     _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
0213     BANIAS(1000),
0214     BANIAS(1100),
0215     BANIAS(1200),
0216     BANIAS(1300),
0217     BANIAS(1400),
0218     BANIAS(1500),
0219     BANIAS(1600),
0220     BANIAS(1700),
0221 
0222     /* NULL model_name is a wildcard */
0223     { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
0224     { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
0225     { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
0226     { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
0227     { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
0228 
0229     { NULL, }
0230 };
0231 #undef _BANIAS
0232 #undef BANIAS
0233 
0234 static int centrino_cpu_init_table(struct cpufreq_policy *policy)
0235 {
0236     struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
0237     struct cpu_model *model;
0238 
0239     for(model = models; model->cpu_id != NULL; model++)
0240         if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
0241             (model->model_name == NULL ||
0242              strcmp(cpu->x86_model_id, model->model_name) == 0))
0243             break;
0244 
0245     if (model->cpu_id == NULL) {
0246         /* No match at all */
0247         pr_debug("no support for CPU model \"%s\": "
0248                "send /proc/cpuinfo to " MAINTAINER "\n",
0249                cpu->x86_model_id);
0250         return -ENOENT;
0251     }
0252 
0253     if (model->op_points == NULL) {
0254         /* Matched a non-match */
0255         pr_debug("no table support for CPU model \"%s\"\n",
0256                cpu->x86_model_id);
0257         pr_debug("try using the acpi-cpufreq driver\n");
0258         return -ENOENT;
0259     }
0260 
0261     per_cpu(centrino_model, policy->cpu) = model;
0262 
0263     pr_debug("found \"%s\": max frequency: %dkHz\n",
0264            model->model_name, model->max_freq);
0265 
0266     return 0;
0267 }
0268 
0269 #else
0270 static inline int centrino_cpu_init_table(struct cpufreq_policy *policy)
0271 {
0272     return -ENODEV;
0273 }
0274 #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
0275 
0276 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
0277                   const struct cpu_id *x)
0278 {
0279     if ((c->x86 == x->x86) &&
0280         (c->x86_model == x->x86_model) &&
0281         (c->x86_stepping == x->x86_stepping))
0282         return 1;
0283     return 0;
0284 }
0285 
0286 /* To be called only after centrino_model is initialized */
0287 static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
0288 {
0289     int i;
0290 
0291     /*
0292      * Extract clock in kHz from PERF_CTL value
0293      * for centrino, as some DSDTs are buggy.
0294      * Ideally, this can be done using the acpi_data structure.
0295      */
0296     if ((per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_BANIAS]) ||
0297         (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_A1]) ||
0298         (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_B0])) {
0299         msr = (msr >> 8) & 0xff;
0300         return msr * 100000;
0301     }
0302 
0303     if ((!per_cpu(centrino_model, cpu)) ||
0304         (!per_cpu(centrino_model, cpu)->op_points))
0305         return 0;
0306 
0307     msr &= 0xffff;
0308     for (i = 0;
0309         per_cpu(centrino_model, cpu)->op_points[i].frequency
0310                             != CPUFREQ_TABLE_END;
0311          i++) {
0312         if (msr == per_cpu(centrino_model, cpu)->op_points[i].driver_data)
0313             return per_cpu(centrino_model, cpu)->
0314                             op_points[i].frequency;
0315     }
0316     if (failsafe)
0317         return per_cpu(centrino_model, cpu)->op_points[i-1].frequency;
0318     else
0319         return 0;
0320 }
0321 
0322 /* Return the current CPU frequency in kHz */
0323 static unsigned int get_cur_freq(unsigned int cpu)
0324 {
0325     unsigned l, h;
0326     unsigned clock_freq;
0327 
0328     rdmsr_on_cpu(cpu, MSR_IA32_PERF_STATUS, &l, &h);
0329     clock_freq = extract_clock(l, cpu, 0);
0330 
0331     if (unlikely(clock_freq == 0)) {
0332         /*
0333          * On some CPUs, we can see transient MSR values (which are
0334          * not present in _PSS), while CPU is doing some automatic
0335          * P-state transition (like TM2). Get the last freq set 
0336          * in PERF_CTL.
0337          */
0338         rdmsr_on_cpu(cpu, MSR_IA32_PERF_CTL, &l, &h);
0339         clock_freq = extract_clock(l, cpu, 1);
0340     }
0341     return clock_freq;
0342 }
0343 
0344 
0345 static int centrino_cpu_init(struct cpufreq_policy *policy)
0346 {
0347     struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
0348     unsigned l, h;
0349     int i;
0350 
0351     /* Only Intel makes Enhanced Speedstep-capable CPUs */
0352     if (cpu->x86_vendor != X86_VENDOR_INTEL ||
0353         !cpu_has(cpu, X86_FEATURE_EST))
0354         return -ENODEV;
0355 
0356     if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
0357         centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
0358 
0359     if (policy->cpu != 0)
0360         return -ENODEV;
0361 
0362     for (i = 0; i < N_IDS; i++)
0363         if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
0364             break;
0365 
0366     if (i != N_IDS)
0367         per_cpu(centrino_cpu, policy->cpu) = &cpu_ids[i];
0368 
0369     if (!per_cpu(centrino_cpu, policy->cpu)) {
0370         pr_debug("found unsupported CPU with "
0371         "Enhanced SpeedStep: send /proc/cpuinfo to "
0372         MAINTAINER "\n");
0373         return -ENODEV;
0374     }
0375 
0376     if (centrino_cpu_init_table(policy))
0377         return -ENODEV;
0378 
0379     /* Check to see if Enhanced SpeedStep is enabled, and try to
0380        enable it if not. */
0381     rdmsr(MSR_IA32_MISC_ENABLE, l, h);
0382 
0383     if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
0384         l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
0385         pr_debug("trying to enable Enhanced SpeedStep (%x)\n", l);
0386         wrmsr(MSR_IA32_MISC_ENABLE, l, h);
0387 
0388         /* check to see if it stuck */
0389         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
0390         if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
0391             pr_info("couldn't enable Enhanced SpeedStep\n");
0392             return -ENODEV;
0393         }
0394     }
0395 
0396     policy->cpuinfo.transition_latency = 10000;
0397                         /* 10uS transition latency */
0398     policy->freq_table = per_cpu(centrino_model, policy->cpu)->op_points;
0399 
0400     return 0;
0401 }
0402 
0403 static int centrino_cpu_exit(struct cpufreq_policy *policy)
0404 {
0405     unsigned int cpu = policy->cpu;
0406 
0407     if (!per_cpu(centrino_model, cpu))
0408         return -ENODEV;
0409 
0410     per_cpu(centrino_model, cpu) = NULL;
0411 
0412     return 0;
0413 }
0414 
0415 /**
0416  * centrino_target - set a new CPUFreq policy
0417  * @policy: new policy
0418  * @index: index of target frequency
0419  *
0420  * Sets a new CPUFreq policy.
0421  */
0422 static int centrino_target(struct cpufreq_policy *policy, unsigned int index)
0423 {
0424     unsigned int    msr, oldmsr = 0, h = 0, cpu = policy->cpu;
0425     int         retval = 0;
0426     unsigned int        j, first_cpu;
0427     struct cpufreq_frequency_table *op_points;
0428     cpumask_var_t covered_cpus;
0429 
0430     if (unlikely(!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)))
0431         return -ENOMEM;
0432 
0433     if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
0434         retval = -ENODEV;
0435         goto out;
0436     }
0437 
0438     first_cpu = 1;
0439     op_points = &per_cpu(centrino_model, cpu)->op_points[index];
0440     for_each_cpu(j, policy->cpus) {
0441         int good_cpu;
0442 
0443         /*
0444          * Support for SMP systems.
0445          * Make sure we are running on CPU that wants to change freq
0446          */
0447         if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
0448             good_cpu = cpumask_any_and(policy->cpus,
0449                            cpu_online_mask);
0450         else
0451             good_cpu = j;
0452 
0453         if (good_cpu >= nr_cpu_ids) {
0454             pr_debug("couldn't limit to CPUs in this domain\n");
0455             retval = -EAGAIN;
0456             if (first_cpu) {
0457                 /* We haven't started the transition yet. */
0458                 goto out;
0459             }
0460             break;
0461         }
0462 
0463         msr = op_points->driver_data;
0464 
0465         if (first_cpu) {
0466             rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr, &h);
0467             if (msr == (oldmsr & 0xffff)) {
0468                 pr_debug("no change needed - msr was and needs "
0469                     "to be %x\n", oldmsr);
0470                 retval = 0;
0471                 goto out;
0472             }
0473 
0474             first_cpu = 0;
0475             /* all but 16 LSB are reserved, treat them with care */
0476             oldmsr &= ~0xffff;
0477             msr &= 0xffff;
0478             oldmsr |= msr;
0479         }
0480 
0481         wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr, h);
0482         if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
0483             break;
0484 
0485         cpumask_set_cpu(j, covered_cpus);
0486     }
0487 
0488     if (unlikely(retval)) {
0489         /*
0490          * We have failed halfway through the frequency change.
0491          * We have sent callbacks to policy->cpus and
0492          * MSRs have already been written on coverd_cpus.
0493          * Best effort undo..
0494          */
0495 
0496         for_each_cpu(j, covered_cpus)
0497             wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr, h);
0498     }
0499     retval = 0;
0500 
0501 out:
0502     free_cpumask_var(covered_cpus);
0503     return retval;
0504 }
0505 
0506 static struct cpufreq_driver centrino_driver = {
0507     .name       = "centrino", /* should be speedstep-centrino,
0508                      but there's a 16 char limit */
0509     .init       = centrino_cpu_init,
0510     .exit       = centrino_cpu_exit,
0511     .verify     = cpufreq_generic_frequency_table_verify,
0512     .target_index   = centrino_target,
0513     .get        = get_cur_freq,
0514     .attr       = cpufreq_generic_attr,
0515 };
0516 
0517 /*
0518  * This doesn't replace the detailed checks above because
0519  * the generic CPU IDs don't have a way to match for steppings
0520  * or ASCII model IDs.
0521  */
0522 static const struct x86_cpu_id centrino_ids[] = {
0523     X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL,  6,  9, X86_FEATURE_EST, NULL),
0524     X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL,  6, 13, X86_FEATURE_EST, NULL),
0525     X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 15,  3, X86_FEATURE_EST, NULL),
0526     X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 15,  4, X86_FEATURE_EST, NULL),
0527     {}
0528 };
0529 
0530 /**
0531  * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
0532  *
0533  * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
0534  * unsupported devices, -ENOENT if there's no voltage table for this
0535  * particular CPU model, -EINVAL on problems during initiatization,
0536  * and zero on success.
0537  *
0538  * This is quite picky.  Not only does the CPU have to advertise the
0539  * "est" flag in the cpuid capability flags, we look for a specific
0540  * CPU model and stepping, and we need to have the exact model name in
0541  * our voltage tables.  That is, be paranoid about not releasing
0542  * someone's valuable magic smoke.
0543  */
0544 static int __init centrino_init(void)
0545 {
0546     if (!x86_match_cpu(centrino_ids))
0547         return -ENODEV;
0548     return cpufreq_register_driver(&centrino_driver);
0549 }
0550 
0551 static void __exit centrino_exit(void)
0552 {
0553     cpufreq_unregister_driver(&centrino_driver);
0554 }
0555 
0556 MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
0557 MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
0558 MODULE_LICENSE ("GPL");
0559 
0560 late_initcall(centrino_init);
0561 module_exit(centrino_exit);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!