drivers/cpufreq/spear-cpufreq.c

0001 /*
0002  * drivers/cpufreq/spear-cpufreq.c
0003  *
0004  * CPU Frequency Scaling for SPEAr platform
0005  *
0006  * Copyright (C) 2012 ST Microelectronics
0007  * Deepak Sikri <deepak.sikri@st.com>
0008  *
0009  * This file is licensed under the terms of the GNU General Public
0010  * License version 2. This program is licensed "as is" without any
0011  * warranty of any kind, whether express or implied.
0012  */
0013
0014 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0015
0016 #include <linux/clk.h>
0017 #include <linux/cpufreq.h>
0018 #include <linux/err.h>
0019 #include <linux/init.h>
0020 #include <linux/module.h>
0021 #include <linux/of_device.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/slab.h>
0024 #include <linux/types.h>
0025
0026 /* SPEAr CPUFreq driver data structure */
0027 static struct {
0028     struct clk *clk;
0029     unsigned int transition_latency;
0030     struct cpufreq_frequency_table *freq_tbl;
0031     u32 cnt;
0032 } spear_cpufreq;
0033
0034 static struct clk *spear1340_cpu_get_possible_parent(unsigned long newfreq)
0035 {
0036     struct clk *sys_pclk;
0037     int pclk;
0038     /*
0039      * In SPEAr1340, cpu clk's parent sys clk can take input from
0040      * following sources
0041      */
0042     const char *sys_clk_src[] = {
0043         "sys_syn_clk",
0044         "pll1_clk",
0045         "pll2_clk",
0046         "pll3_clk",
0047     };
0048
0049     /*
0050      * As sys clk can have multiple source with their own range
0051      * limitation so we choose possible sources accordingly
0052      */
0053     if (newfreq <= 300000000)
0054         pclk = 0; /* src is sys_syn_clk */
0055     else if (newfreq > 300000000 && newfreq <= 500000000)
0056         pclk = 3; /* src is pll3_clk */
0057     else if (newfreq == 600000000)
0058         pclk = 1; /* src is pll1_clk */
0059     else
0060         return ERR_PTR(-EINVAL);
0061
0062     /* Get parent to sys clock */
0063     sys_pclk = clk_get(NULL, sys_clk_src[pclk]);
0064     if (IS_ERR(sys_pclk))
0065         pr_err("Failed to get %s clock\n", sys_clk_src[pclk]);
0066
0067     return sys_pclk;
0068 }
0069
0070 /*
0071  * In SPEAr1340, we cannot use newfreq directly because we need to actually
0072  * access a source clock (clk) which might not be ancestor of cpu at present.
0073  * Hence in SPEAr1340 we would operate on source clock directly before switching
0074  * cpu clock to it.
0075  */
0076 static int spear1340_set_cpu_rate(struct clk *sys_pclk, unsigned long newfreq)
0077 {
0078     struct clk *sys_clk;
0079     int ret = 0;
0080
0081     sys_clk = clk_get_parent(spear_cpufreq.clk);
0082     if (IS_ERR(sys_clk)) {
0083         pr_err("failed to get cpu's parent (sys) clock\n");
0084         return PTR_ERR(sys_clk);
0085     }
0086
0087     /* Set the rate of the source clock before changing the parent */
0088     ret = clk_set_rate(sys_pclk, newfreq);
0089     if (ret) {
0090         pr_err("Failed to set sys clk rate to %lu\n", newfreq);
0091         return ret;
0092     }
0093
0094     ret = clk_set_parent(sys_clk, sys_pclk);
0095     if (ret) {
0096         pr_err("Failed to set sys clk parent\n");
0097         return ret;
0098     }
0099
0100     return 0;
0101 }
0102
0103 static int spear_cpufreq_target(struct cpufreq_policy *policy,
0104         unsigned int index)
0105 {
0106     long newfreq;
0107     struct clk *srcclk;
0108     int ret, mult = 1;
0109
0110     newfreq = spear_cpufreq.freq_tbl[index].frequency * 1000;
0111
0112     if (of_machine_is_compatible("st,spear1340")) {
0113         /*
0114          * SPEAr1340 is special in the sense that due to the possibility
0115          * of multiple clock sources for cpu clk's parent we can have
0116          * different clock source for different frequency of cpu clk.
0117          * Hence we need to choose one from amongst these possible clock
0118          * sources.
0119          */
0120         srcclk = spear1340_cpu_get_possible_parent(newfreq);
0121         if (IS_ERR(srcclk)) {
0122             pr_err("Failed to get src clk\n");
0123             return PTR_ERR(srcclk);
0124         }
0125
0126         /* SPEAr1340: src clk is always 2 * intended cpu clk */
0127         mult = 2;
0128     } else {
0129         /*
0130          * src clock to be altered is ancestor of cpu clock. Hence we
0131          * can directly work on cpu clk
0132          */
0133         srcclk = spear_cpufreq.clk;
0134     }
0135
0136     newfreq = clk_round_rate(srcclk, newfreq * mult);
0137     if (newfreq <= 0) {
0138         pr_err("clk_round_rate failed for cpu src clock\n");
0139         return newfreq;
0140     }
0141
0142     if (mult == 2)
0143         ret = spear1340_set_cpu_rate(srcclk, newfreq);
0144     else
0145         ret = clk_set_rate(spear_cpufreq.clk, newfreq);
0146
0147     if (ret)
0148         pr_err("CPU Freq: cpu clk_set_rate failed: %d\n", ret);
0149
0150     return ret;
0151 }
0152
0153 static int spear_cpufreq_init(struct cpufreq_policy *policy)
0154 {
0155     policy->clk = spear_cpufreq.clk;
0156     cpufreq_generic_init(policy, spear_cpufreq.freq_tbl,
0157             spear_cpufreq.transition_latency);
0158     return 0;
0159 }
0160
0161 static struct cpufreq_driver spear_cpufreq_driver = {
0162     .name       = "cpufreq-spear",
0163     .flags      = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
0164     .verify     = cpufreq_generic_frequency_table_verify,
0165     .target_index   = spear_cpufreq_target,
0166     .get        = cpufreq_generic_get,
0167     .init       = spear_cpufreq_init,
0168     .attr       = cpufreq_generic_attr,
0169 };
0170
0171 static int spear_cpufreq_probe(struct platform_device *pdev)
0172 {
0173     struct device_node *np;
0174     const struct property *prop;
0175     struct cpufreq_frequency_table *freq_tbl;
0176     const __be32 *val;
0177     int cnt, i, ret;
0178
0179     np = of_cpu_device_node_get(0);
0180     if (!np) {
0181         pr_err("No cpu node found\n");
0182         return -ENODEV;
0183     }
0184
0185     if (of_property_read_u32(np, "clock-latency",
0186                 &spear_cpufreq.transition_latency))
0187         spear_cpufreq.transition_latency = CPUFREQ_ETERNAL;
0188
0189     prop = of_find_property(np, "cpufreq_tbl", NULL);
0190     if (!prop || !prop->value) {
0191         pr_err("Invalid cpufreq_tbl\n");
0192         ret = -ENODEV;
0193         goto out_put_node;
0194     }
0195
0196     cnt = prop->length / sizeof(u32);
0197     val = prop->value;
0198
0199     freq_tbl = kcalloc(cnt + 1, sizeof(*freq_tbl), GFP_KERNEL);
0200     if (!freq_tbl) {
0201         ret = -ENOMEM;
0202         goto out_put_node;
0203     }
0204
0205     for (i = 0; i < cnt; i++)
0206         freq_tbl[i].frequency = be32_to_cpup(val++);
0207
0208     freq_tbl[i].frequency = CPUFREQ_TABLE_END;
0209
0210     spear_cpufreq.freq_tbl = freq_tbl;
0211
0212     of_node_put(np);
0213
0214     spear_cpufreq.clk = clk_get(NULL, "cpu_clk");
0215     if (IS_ERR(spear_cpufreq.clk)) {
0216         pr_err("Unable to get CPU clock\n");
0217         ret = PTR_ERR(spear_cpufreq.clk);
0218         goto out_put_mem;
0219     }
0220
0221     ret = cpufreq_register_driver(&spear_cpufreq_driver);
0222     if (!ret)
0223         return 0;
0224
0225     pr_err("failed register driver: %d\n", ret);
0226     clk_put(spear_cpufreq.clk);
0227
0228 out_put_mem:
0229     kfree(freq_tbl);
0230     return ret;
0231
0232 out_put_node:
0233     of_node_put(np);
0234     return ret;
0235 }
0236
0237 static struct platform_driver spear_cpufreq_platdrv = {
0238     .driver = {
0239         .name   = "spear-cpufreq",
0240     },
0241     .probe      = spear_cpufreq_probe,
0242 };
0243 module_platform_driver(spear_cpufreq_platdrv);
0244
0245 MODULE_AUTHOR("Deepak Sikri <deepak.sikri@st.com>");
0246 MODULE_DESCRIPTION("SPEAr CPUFreq driver");
0247 MODULE_LICENSE("GPL");