drivers/cpufreq/s3c24xx-cpufreq.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2006-2008 Simtec Electronics
0004  *  http://armlinux.simtec.co.uk/
0005  *  Ben Dooks <ben@simtec.co.uk>
0006  *
0007  * S3C24XX CPU Frequency scaling
0008 */
0009
0010 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0011
0012 #include <linux/init.h>
0013 #include <linux/module.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/ioport.h>
0016 #include <linux/cpufreq.h>
0017 #include <linux/cpu.h>
0018 #include <linux/clk.h>
0019 #include <linux/err.h>
0020 #include <linux/io.h>
0021 #include <linux/device.h>
0022 #include <linux/sysfs.h>
0023 #include <linux/slab.h>
0024 #include <linux/soc/samsung/s3c-cpufreq-core.h>
0025 #include <linux/soc/samsung/s3c-pm.h>
0026
0027 #include <asm/mach/arch.h>
0028 #include <asm/mach/map.h>
0029
0030 /* note, cpufreq support deals in kHz, no Hz */
0031 static struct cpufreq_driver s3c24xx_driver;
0032 static struct s3c_cpufreq_config cpu_cur;
0033 static struct s3c_iotimings s3c24xx_iotiming;
0034 static struct cpufreq_frequency_table *pll_reg;
0035 static unsigned int last_target = ~0;
0036 static unsigned int ftab_size;
0037 static struct cpufreq_frequency_table *ftab;
0038
0039 static struct clk *_clk_mpll;
0040 static struct clk *_clk_xtal;
0041 static struct clk *clk_fclk;
0042 static struct clk *clk_hclk;
0043 static struct clk *clk_pclk;
0044 static struct clk *clk_arm;
0045
0046 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS
0047 struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void)
0048 {
0049     return &cpu_cur;
0050 }
0051
0052 struct s3c_iotimings *s3c_cpufreq_getiotimings(void)
0053 {
0054     return &s3c24xx_iotiming;
0055 }
0056 #endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS */
0057
0058 static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg)
0059 {
0060     unsigned long fclk, pclk, hclk, armclk;
0061
0062     cfg->freq.fclk = fclk = clk_get_rate(clk_fclk);
0063     cfg->freq.hclk = hclk = clk_get_rate(clk_hclk);
0064     cfg->freq.pclk = pclk = clk_get_rate(clk_pclk);
0065     cfg->freq.armclk = armclk = clk_get_rate(clk_arm);
0066
0067     cfg->pll.driver_data = s3c24xx_read_mpllcon();
0068     cfg->pll.frequency = fclk;
0069
0070     cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
0071
0072     cfg->divs.h_divisor = fclk / hclk;
0073     cfg->divs.p_divisor = fclk / pclk;
0074 }
0075
0076 static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg)
0077 {
0078     unsigned long pll = cfg->pll.frequency;
0079
0080     cfg->freq.fclk = pll;
0081     cfg->freq.hclk = pll / cfg->divs.h_divisor;
0082     cfg->freq.pclk = pll / cfg->divs.p_divisor;
0083
0084     /* convert hclk into 10ths of nanoseconds for io calcs */
0085     cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
0086 }
0087
0088 static inline int closer(unsigned int target, unsigned int n, unsigned int c)
0089 {
0090     int diff_cur = abs(target - c);
0091     int diff_new = abs(target - n);
0092
0093     return (diff_new < diff_cur);
0094 }
0095
0096 static void s3c_cpufreq_show(const char *pfx,
0097                  struct s3c_cpufreq_config *cfg)
0098 {
0099     s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n",
0100              pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk,
0101              cfg->freq.hclk, cfg->divs.h_divisor,
0102              cfg->freq.pclk, cfg->divs.p_divisor);
0103 }
0104
0105 /* functions to wrapper the driver info calls to do the cpu specific work */
0106
0107 static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg)
0108 {
0109     if (cfg->info->set_iotiming)
0110         (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming);
0111 }
0112
0113 static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg)
0114 {
0115     if (cfg->info->calc_iotiming)
0116         return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming);
0117
0118     return 0;
0119 }
0120
0121 static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
0122 {
0123     (cfg->info->set_refresh)(cfg);
0124 }
0125
0126 static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
0127 {
0128     (cfg->info->set_divs)(cfg);
0129 }
0130
0131 static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
0132 {
0133     return (cfg->info->calc_divs)(cfg);
0134 }
0135
0136 static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg)
0137 {
0138     cfg->mpll = _clk_mpll;
0139     (cfg->info->set_fvco)(cfg);
0140 }
0141
0142 static inline void s3c_cpufreq_updateclk(struct clk *clk,
0143                      unsigned int freq)
0144 {
0145     clk_set_rate(clk, freq);
0146 }
0147
0148 static int s3c_cpufreq_settarget(struct cpufreq_policy *policy,
0149                  unsigned int target_freq,
0150                  struct cpufreq_frequency_table *pll)
0151 {
0152     struct s3c_cpufreq_freqs freqs;
0153     struct s3c_cpufreq_config cpu_new;
0154     unsigned long flags;
0155
0156     cpu_new = cpu_cur;  /* copy new from current */
0157
0158     s3c_cpufreq_show("cur", &cpu_cur);
0159
0160     /* TODO - check for DMA currently outstanding */
0161
0162     cpu_new.pll = pll ? *pll : cpu_cur.pll;
0163
0164     if (pll)
0165         freqs.pll_changing = 1;
0166
0167     /* update our frequencies */
0168
0169     cpu_new.freq.armclk = target_freq;
0170     cpu_new.freq.fclk = cpu_new.pll.frequency;
0171
0172     if (s3c_cpufreq_calcdivs(&cpu_new) < 0) {
0173         pr_err("no divisors for %d\n", target_freq);
0174         goto err_notpossible;
0175     }
0176
0177     s3c_freq_dbg("%s: got divs\n", __func__);
0178
0179     s3c_cpufreq_calc(&cpu_new);
0180
0181     s3c_freq_dbg("%s: calculated frequencies for new\n", __func__);
0182
0183     if (cpu_new.freq.hclk != cpu_cur.freq.hclk) {
0184         if (s3c_cpufreq_calcio(&cpu_new) < 0) {
0185             pr_err("%s: no IO timings\n", __func__);
0186             goto err_notpossible;
0187         }
0188     }
0189
0190     s3c_cpufreq_show("new", &cpu_new);
0191
0192     /* setup our cpufreq parameters */
0193
0194     freqs.old = cpu_cur.freq;
0195     freqs.new = cpu_new.freq;
0196
0197     freqs.freqs.old = cpu_cur.freq.armclk / 1000;
0198     freqs.freqs.new = cpu_new.freq.armclk / 1000;
0199
0200     /* update f/h/p clock settings before we issue the change
0201      * notification, so that drivers do not need to do anything
0202      * special if they want to recalculate on CPUFREQ_PRECHANGE. */
0203
0204     s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency);
0205     s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk);
0206     s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk);
0207     s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk);
0208
0209     /* start the frequency change */
0210     cpufreq_freq_transition_begin(policy, &freqs.freqs);
0211
0212     /* If hclk is staying the same, then we do not need to
0213      * re-write the IO or the refresh timings whilst we are changing
0214      * speed. */
0215
0216     local_irq_save(flags);
0217
0218     /* is our memory clock slowing down? */
0219     if (cpu_new.freq.hclk < cpu_cur.freq.hclk) {
0220         s3c_cpufreq_setrefresh(&cpu_new);
0221         s3c_cpufreq_setio(&cpu_new);
0222     }
0223
0224     if (cpu_new.freq.fclk == cpu_cur.freq.fclk) {
0225         /* not changing PLL, just set the divisors */
0226
0227         s3c_cpufreq_setdivs(&cpu_new);
0228     } else {
0229         if (cpu_new.freq.fclk < cpu_cur.freq.fclk) {
0230             /* slow the cpu down, then set divisors */
0231
0232             s3c_cpufreq_setfvco(&cpu_new);
0233             s3c_cpufreq_setdivs(&cpu_new);
0234         } else {
0235             /* set the divisors, then speed up */
0236
0237             s3c_cpufreq_setdivs(&cpu_new);
0238             s3c_cpufreq_setfvco(&cpu_new);
0239         }
0240     }
0241
0242     /* did our memory clock speed up */
0243     if (cpu_new.freq.hclk > cpu_cur.freq.hclk) {
0244         s3c_cpufreq_setrefresh(&cpu_new);
0245         s3c_cpufreq_setio(&cpu_new);
0246     }
0247
0248     /* update our current settings */
0249     cpu_cur = cpu_new;
0250
0251     local_irq_restore(flags);
0252
0253     /* notify everyone we've done this */
0254     cpufreq_freq_transition_end(policy, &freqs.freqs, 0);
0255
0256     s3c_freq_dbg("%s: finished\n", __func__);
0257     return 0;
0258
0259  err_notpossible:
0260     pr_err("no compatible settings for %d\n", target_freq);
0261     return -EINVAL;
0262 }
0263
0264 /* s3c_cpufreq_target
0265  *
0266  * called by the cpufreq core to adjust the frequency that the CPU
0267  * is currently running at.
0268  */
0269
0270 static int s3c_cpufreq_target(struct cpufreq_policy *policy,
0271                   unsigned int target_freq,
0272                   unsigned int relation)
0273 {
0274     struct cpufreq_frequency_table *pll;
0275     unsigned int index;
0276
0277     /* avoid repeated calls which cause a needless amout of duplicated
0278      * logging output (and CPU time as the calculation process is
0279      * done) */
0280     if (target_freq == last_target)
0281         return 0;
0282
0283     last_target = target_freq;
0284
0285     s3c_freq_dbg("%s: policy %p, target %u, relation %u\n",
0286              __func__, policy, target_freq, relation);
0287
0288     if (ftab) {
0289         index = cpufreq_frequency_table_target(policy, target_freq,
0290                                relation);
0291
0292         s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__,
0293                  target_freq, index, ftab[index].frequency);
0294         target_freq = ftab[index].frequency;
0295     }
0296
0297     target_freq *= 1000;  /* convert target to Hz */
0298
0299     /* find the settings for our new frequency */
0300
0301     if (!pll_reg || cpu_cur.lock_pll) {
0302         /* either we've not got any PLL values, or we've locked
0303          * to the current one. */
0304         pll = NULL;
0305     } else {
0306         struct cpufreq_policy tmp_policy;
0307
0308         /* we keep the cpu pll table in Hz, to ensure we get an
0309          * accurate value for the PLL output. */
0310
0311         tmp_policy.min = policy->min * 1000;
0312         tmp_policy.max = policy->max * 1000;
0313         tmp_policy.cpu = policy->cpu;
0314         tmp_policy.freq_table = pll_reg;
0315
0316         /* cpufreq_frequency_table_target returns the index
0317          * of the table entry, not the value of
0318          * the table entry's index field. */
0319
0320         index = cpufreq_frequency_table_target(&tmp_policy, target_freq,
0321                                relation);
0322         pll = pll_reg + index;
0323
0324         s3c_freq_dbg("%s: target %u => %u\n",
0325                  __func__, target_freq, pll->frequency);
0326
0327         target_freq = pll->frequency;
0328     }
0329
0330     return s3c_cpufreq_settarget(policy, target_freq, pll);
0331 }
0332
0333 struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name)
0334 {
0335     struct clk *clk;
0336
0337     clk = clk_get(dev, name);
0338     if (IS_ERR(clk))
0339         pr_err("failed to get clock '%s'\n", name);
0340
0341     return clk;
0342 }
0343
0344 static int s3c_cpufreq_init(struct cpufreq_policy *policy)
0345 {
0346     policy->clk = clk_arm;
0347     policy->cpuinfo.transition_latency = cpu_cur.info->latency;
0348     policy->freq_table = ftab;
0349
0350     return 0;
0351 }
0352
0353 static int __init s3c_cpufreq_initclks(void)
0354 {
0355     _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll");
0356     _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal");
0357     clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk");
0358     clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk");
0359     clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk");
0360     clk_arm = s3c_cpufreq_clk_get(NULL, "armclk");
0361
0362     if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) ||
0363         IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) {
0364         pr_err("%s: could not get clock(s)\n", __func__);
0365         return -ENOENT;
0366     }
0367
0368     pr_info("%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n",
0369         __func__,
0370         clk_get_rate(clk_fclk) / 1000,
0371         clk_get_rate(clk_hclk) / 1000,
0372         clk_get_rate(clk_pclk) / 1000,
0373         clk_get_rate(clk_arm) / 1000);
0374
0375     return 0;
0376 }
0377
0378 #ifdef CONFIG_PM
0379 static struct cpufreq_frequency_table suspend_pll;
0380 static unsigned int suspend_freq;
0381
0382 static int s3c_cpufreq_suspend(struct cpufreq_policy *policy)
0383 {
0384     suspend_pll.frequency = clk_get_rate(_clk_mpll);
0385     suspend_pll.driver_data = s3c24xx_read_mpllcon();
0386     suspend_freq = clk_get_rate(clk_arm);
0387
0388     return 0;
0389 }
0390
0391 static int s3c_cpufreq_resume(struct cpufreq_policy *policy)
0392 {
0393     int ret;
0394
0395     s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy);
0396
0397     last_target = ~0;   /* invalidate last_target setting */
0398
0399     /* whilst we will be called later on, we try and re-set the
0400      * cpu frequencies as soon as possible so that we do not end
0401      * up resuming devices and then immediately having to re-set
0402      * a number of settings once these devices have restarted.
0403      *
0404      * as a note, it is expected devices are not used until they
0405      * have been un-suspended and at that time they should have
0406      * used the updated clock settings.
0407      */
0408
0409     ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll);
0410     if (ret) {
0411         pr_err("%s: failed to reset pll/freq\n", __func__);
0412         return ret;
0413     }
0414
0415     return 0;
0416 }
0417 #else
0418 #define s3c_cpufreq_resume NULL
0419 #define s3c_cpufreq_suspend NULL
0420 #endif
0421
0422 static struct cpufreq_driver s3c24xx_driver = {
0423     .flags      = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
0424     .target     = s3c_cpufreq_target,
0425     .get        = cpufreq_generic_get,
0426     .init       = s3c_cpufreq_init,
0427     .suspend    = s3c_cpufreq_suspend,
0428     .resume     = s3c_cpufreq_resume,
0429     .name       = "s3c24xx",
0430 };
0431
0432
0433 int s3c_cpufreq_register(struct s3c_cpufreq_info *info)
0434 {
0435     if (!info || !info->name) {
0436         pr_err("%s: failed to pass valid information\n", __func__);
0437         return -EINVAL;
0438     }
0439
0440     pr_info("S3C24XX CPU Frequency driver, %s cpu support\n",
0441         info->name);
0442
0443     /* check our driver info has valid data */
0444
0445     BUG_ON(info->set_refresh == NULL);
0446     BUG_ON(info->set_divs == NULL);
0447     BUG_ON(info->calc_divs == NULL);
0448
0449     /* info->set_fvco is optional, depending on whether there
0450      * is a need to set the clock code. */
0451
0452     cpu_cur.info = info;
0453
0454     /* Note, driver registering should probably update locktime */
0455
0456     return 0;
0457 }
0458
0459 int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
0460 {
0461     struct s3c_cpufreq_board *ours;
0462
0463     if (!board) {
0464         pr_info("%s: no board data\n", __func__);
0465         return -EINVAL;
0466     }
0467
0468     /* Copy the board information so that each board can make this
0469      * initdata. */
0470
0471     ours = kzalloc(sizeof(*ours), GFP_KERNEL);
0472     if (!ours)
0473         return -ENOMEM;
0474
0475     *ours = *board;
0476     cpu_cur.board = ours;
0477
0478     return 0;
0479 }
0480
0481 static int __init s3c_cpufreq_auto_io(void)
0482 {
0483     int ret;
0484
0485     if (!cpu_cur.info->get_iotiming) {
0486         pr_err("%s: get_iotiming undefined\n", __func__);
0487         return -ENOENT;
0488     }
0489
0490     pr_info("%s: working out IO settings\n", __func__);
0491
0492     ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming);
0493     if (ret)
0494         pr_err("%s: failed to get timings\n", __func__);
0495
0496     return ret;
0497 }
0498
0499 /* if one or is zero, then return the other, otherwise return the min */
0500 #define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b))
0501
0502 /**
0503  * s3c_cpufreq_freq_min - find the minimum settings for the given freq.
0504  * @dst: The destination structure
0505  * @a: One argument.
0506  * @b: The other argument.
0507  *
0508  * Create a minimum of each frequency entry in the 'struct s3c_freq',
0509  * unless the entry is zero when it is ignored and the non-zero argument
0510  * used.
0511  */
0512 static void s3c_cpufreq_freq_min(struct s3c_freq *dst,
0513                  struct s3c_freq *a, struct s3c_freq *b)
0514 {
0515     dst->fclk = do_min(a->fclk, b->fclk);
0516     dst->hclk = do_min(a->hclk, b->hclk);
0517     dst->pclk = do_min(a->pclk, b->pclk);
0518     dst->armclk = do_min(a->armclk, b->armclk);
0519 }
0520
0521 static inline u32 calc_locktime(u32 freq, u32 time_us)
0522 {
0523     u32 result;
0524
0525     result = freq * time_us;
0526     result = DIV_ROUND_UP(result, 1000 * 1000);
0527
0528     return result;
0529 }
0530
0531 static void s3c_cpufreq_update_loctkime(void)
0532 {
0533     unsigned int bits = cpu_cur.info->locktime_bits;
0534     u32 rate = (u32)clk_get_rate(_clk_xtal);
0535     u32 val;
0536
0537     if (bits == 0) {
0538         WARN_ON(1);
0539         return;
0540     }
0541
0542     val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits;
0543     val |= calc_locktime(rate, cpu_cur.info->locktime_m);
0544
0545     pr_info("%s: new locktime is 0x%08x\n", __func__, val);
0546     s3c24xx_write_locktime(val);
0547 }
0548
0549 static int s3c_cpufreq_build_freq(void)
0550 {
0551     int size, ret;
0552
0553     kfree(ftab);
0554
0555     size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0);
0556     size++;
0557
0558     ftab = kcalloc(size, sizeof(*ftab), GFP_KERNEL);
0559     if (!ftab)
0560         return -ENOMEM;
0561
0562     ftab_size = size;
0563
0564     ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size);
0565     s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END);
0566
0567     return 0;
0568 }
0569
0570 static int __init s3c_cpufreq_initcall(void)
0571 {
0572     int ret = 0;
0573
0574     if (cpu_cur.info && cpu_cur.board) {
0575         ret = s3c_cpufreq_initclks();
0576         if (ret)
0577             goto out;
0578
0579         /* get current settings */
0580         s3c_cpufreq_getcur(&cpu_cur);
0581         s3c_cpufreq_show("cur", &cpu_cur);
0582
0583         if (cpu_cur.board->auto_io) {
0584             ret = s3c_cpufreq_auto_io();
0585             if (ret) {
0586                 pr_err("%s: failed to get io timing\n",
0587                        __func__);
0588                 goto out;
0589             }
0590         }
0591
0592         if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) {
0593             pr_err("%s: no IO support registered\n", __func__);
0594             ret = -EINVAL;
0595             goto out;
0596         }
0597
0598         if (!cpu_cur.info->need_pll)
0599             cpu_cur.lock_pll = 1;
0600
0601         s3c_cpufreq_update_loctkime();
0602
0603         s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max,
0604                      &cpu_cur.info->max);
0605
0606         if (cpu_cur.info->calc_freqtable)
0607             s3c_cpufreq_build_freq();
0608
0609         ret = cpufreq_register_driver(&s3c24xx_driver);
0610     }
0611
0612  out:
0613     return ret;
0614 }
0615
0616 late_initcall(s3c_cpufreq_initcall);
0617
0618 /**
0619  * s3c_plltab_register - register CPU PLL table.
0620  * @plls: The list of PLL entries.
0621  * @plls_no: The size of the PLL entries @plls.
0622  *
0623  * Register the given set of PLLs with the system.
0624  */
0625 int s3c_plltab_register(struct cpufreq_frequency_table *plls,
0626                    unsigned int plls_no)
0627 {
0628     struct cpufreq_frequency_table *vals;
0629     unsigned int size;
0630
0631     size = sizeof(*vals) * (plls_no + 1);
0632
0633     vals = kzalloc(size, GFP_KERNEL);
0634     if (vals) {
0635         memcpy(vals, plls, size);
0636         pll_reg = vals;
0637
0638         /* write a terminating entry, we don't store it in the
0639          * table that is stored in the kernel */
0640         vals += plls_no;
0641         vals->frequency = CPUFREQ_TABLE_END;
0642
0643         pr_info("%d PLL entries\n", plls_no);
0644     } else
0645         pr_err("no memory for PLL tables\n");
0646
0647     return vals ? 0 : -ENOMEM;
0648 }