drivers/cpufreq/qcom-cpufreq-nvmem.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
0004  */
0005
0006 /*
0007  * In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
0008  * the CPU frequency subset and voltage value of each OPP varies
0009  * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
0010  * defines the voltage and frequency value based on the msm-id in SMEM
0011  * and speedbin blown in the efuse combination.
0012  * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
0013  * to provide the OPP framework with required information.
0014  * This is used to determine the voltage and frequency value for each OPP of
0015  * operating-points-v2 table when it is parsed by the OPP framework.
0016  */
0017
0018 #include <linux/cpu.h>
0019 #include <linux/err.h>
0020 #include <linux/init.h>
0021 #include <linux/kernel.h>
0022 #include <linux/module.h>
0023 #include <linux/nvmem-consumer.h>
0024 #include <linux/of.h>
0025 #include <linux/of_device.h>
0026 #include <linux/platform_device.h>
0027 #include <linux/pm_domain.h>
0028 #include <linux/pm_opp.h>
0029 #include <linux/slab.h>
0030 #include <linux/soc/qcom/smem.h>
0031
0032 #define MSM_ID_SMEM 137
0033
0034 enum _msm_id {
0035     MSM8996V3 = 0xF6ul,
0036     APQ8096V3 = 0x123ul,
0037     MSM8996SG = 0x131ul,
0038     APQ8096SG = 0x138ul,
0039 };
0040
0041 enum _msm8996_version {
0042     MSM8996_V3,
0043     MSM8996_SG,
0044     NUM_OF_MSM8996_VERSIONS,
0045 };
0046
0047 struct qcom_cpufreq_drv;
0048
0049 struct qcom_cpufreq_match_data {
0050     int (*get_version)(struct device *cpu_dev,
0051                struct nvmem_cell *speedbin_nvmem,
0052                char **pvs_name,
0053                struct qcom_cpufreq_drv *drv);
0054     const char **genpd_names;
0055 };
0056
0057 struct qcom_cpufreq_drv {
0058     int *opp_tokens;
0059     u32 versions;
0060     const struct qcom_cpufreq_match_data *data;
0061 };
0062
0063 static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev;
0064
0065 static void get_krait_bin_format_a(struct device *cpu_dev,
0066                       int *speed, int *pvs, int *pvs_ver,
0067                       struct nvmem_cell *pvs_nvmem, u8 *buf)
0068 {
0069     u32 pte_efuse;
0070
0071     pte_efuse = *((u32 *)buf);
0072
0073     *speed = pte_efuse & 0xf;
0074     if (*speed == 0xf)
0075         *speed = (pte_efuse >> 4) & 0xf;
0076
0077     if (*speed == 0xf) {
0078         *speed = 0;
0079         dev_warn(cpu_dev, "Speed bin: Defaulting to %d\n", *speed);
0080     } else {
0081         dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
0082     }
0083
0084     *pvs = (pte_efuse >> 10) & 0x7;
0085     if (*pvs == 0x7)
0086         *pvs = (pte_efuse >> 13) & 0x7;
0087
0088     if (*pvs == 0x7) {
0089         *pvs = 0;
0090         dev_warn(cpu_dev, "PVS bin: Defaulting to %d\n", *pvs);
0091     } else {
0092         dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
0093     }
0094 }
0095
0096 static void get_krait_bin_format_b(struct device *cpu_dev,
0097                       int *speed, int *pvs, int *pvs_ver,
0098                       struct nvmem_cell *pvs_nvmem, u8 *buf)
0099 {
0100     u32 pte_efuse, redundant_sel;
0101
0102     pte_efuse = *((u32 *)buf);
0103     redundant_sel = (pte_efuse >> 24) & 0x7;
0104
0105     *pvs_ver = (pte_efuse >> 4) & 0x3;
0106
0107     switch (redundant_sel) {
0108     case 1:
0109         *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
0110         *speed = (pte_efuse >> 27) & 0xf;
0111         break;
0112     case 2:
0113         *pvs = (pte_efuse >> 27) & 0xf;
0114         *speed = pte_efuse & 0x7;
0115         break;
0116     default:
0117         /* 4 bits of PVS are in efuse register bits 31, 8-6. */
0118         *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
0119         *speed = pte_efuse & 0x7;
0120     }
0121
0122     /* Check SPEED_BIN_BLOW_STATUS */
0123     if (pte_efuse & BIT(3)) {
0124         dev_dbg(cpu_dev, "Speed bin: %d\n", *speed);
0125     } else {
0126         dev_warn(cpu_dev, "Speed bin not set. Defaulting to 0!\n");
0127         *speed = 0;
0128     }
0129
0130     /* Check PVS_BLOW_STATUS */
0131     pte_efuse = *(((u32 *)buf) + 1);
0132     pte_efuse &= BIT(21);
0133     if (pte_efuse) {
0134         dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs);
0135     } else {
0136         dev_warn(cpu_dev, "PVS bin not set. Defaulting to 0!\n");
0137         *pvs = 0;
0138     }
0139
0140     dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
0141 }
0142
0143 static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
0144 {
0145     size_t len;
0146     u32 *msm_id;
0147     enum _msm8996_version version;
0148
0149     msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len);
0150     if (IS_ERR(msm_id))
0151         return NUM_OF_MSM8996_VERSIONS;
0152
0153     /* The first 4 bytes are format, next to them is the actual msm-id */
0154     msm_id++;
0155
0156     switch ((enum _msm_id)*msm_id) {
0157     case MSM8996V3:
0158     case APQ8096V3:
0159         version = MSM8996_V3;
0160         break;
0161     case MSM8996SG:
0162     case APQ8096SG:
0163         version = MSM8996_SG;
0164         break;
0165     default:
0166         version = NUM_OF_MSM8996_VERSIONS;
0167     }
0168
0169     return version;
0170 }
0171
0172 static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
0173                       struct nvmem_cell *speedbin_nvmem,
0174                       char **pvs_name,
0175                       struct qcom_cpufreq_drv *drv)
0176 {
0177     size_t len;
0178     u8 *speedbin;
0179     enum _msm8996_version msm8996_version;
0180     *pvs_name = NULL;
0181
0182     msm8996_version = qcom_cpufreq_get_msm_id();
0183     if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
0184         dev_err(cpu_dev, "Not Snapdragon 820/821!");
0185         return -ENODEV;
0186     }
0187
0188     speedbin = nvmem_cell_read(speedbin_nvmem, &len);
0189     if (IS_ERR(speedbin))
0190         return PTR_ERR(speedbin);
0191
0192     switch (msm8996_version) {
0193     case MSM8996_V3:
0194         drv->versions = 1 << (unsigned int)(*speedbin);
0195         break;
0196     case MSM8996_SG:
0197         drv->versions = 1 << ((unsigned int)(*speedbin) + 4);
0198         break;
0199     default:
0200         BUG();
0201         break;
0202     }
0203
0204     kfree(speedbin);
0205     return 0;
0206 }
0207
0208 static int qcom_cpufreq_krait_name_version(struct device *cpu_dev,
0209                        struct nvmem_cell *speedbin_nvmem,
0210                        char **pvs_name,
0211                        struct qcom_cpufreq_drv *drv)
0212 {
0213     int speed = 0, pvs = 0, pvs_ver = 0;
0214     u8 *speedbin;
0215     size_t len;
0216
0217     speedbin = nvmem_cell_read(speedbin_nvmem, &len);
0218
0219     if (IS_ERR(speedbin))
0220         return PTR_ERR(speedbin);
0221
0222     switch (len) {
0223     case 4:
0224         get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver,
0225                        speedbin_nvmem, speedbin);
0226         break;
0227     case 8:
0228         get_krait_bin_format_b(cpu_dev, &speed, &pvs, &pvs_ver,
0229                        speedbin_nvmem, speedbin);
0230         break;
0231     default:
0232         dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n");
0233         return -ENODEV;
0234     }
0235
0236     snprintf(*pvs_name, sizeof("speedXX-pvsXX-vXX"), "speed%d-pvs%d-v%d",
0237          speed, pvs, pvs_ver);
0238
0239     drv->versions = (1 << speed);
0240
0241     kfree(speedbin);
0242     return 0;
0243 }
0244
0245 static const struct qcom_cpufreq_match_data match_data_kryo = {
0246     .get_version = qcom_cpufreq_kryo_name_version,
0247 };
0248
0249 static const struct qcom_cpufreq_match_data match_data_krait = {
0250     .get_version = qcom_cpufreq_krait_name_version,
0251 };
0252
0253 static const char *qcs404_genpd_names[] = { "cpr", NULL };
0254
0255 static const struct qcom_cpufreq_match_data match_data_qcs404 = {
0256     .genpd_names = qcs404_genpd_names,
0257 };
0258
0259 static int qcom_cpufreq_probe(struct platform_device *pdev)
0260 {
0261     struct qcom_cpufreq_drv *drv;
0262     struct nvmem_cell *speedbin_nvmem;
0263     struct device_node *np;
0264     struct device *cpu_dev;
0265     char *pvs_name = "speedXX-pvsXX-vXX";
0266     unsigned cpu;
0267     const struct of_device_id *match;
0268     int ret;
0269
0270     cpu_dev = get_cpu_device(0);
0271     if (!cpu_dev)
0272         return -ENODEV;
0273
0274     np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
0275     if (!np)
0276         return -ENOENT;
0277
0278     ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
0279     if (!ret) {
0280         of_node_put(np);
0281         return -ENOENT;
0282     }
0283
0284     drv = kzalloc(sizeof(*drv), GFP_KERNEL);
0285     if (!drv)
0286         return -ENOMEM;
0287
0288     match = pdev->dev.platform_data;
0289     drv->data = match->data;
0290     if (!drv->data) {
0291         ret = -ENODEV;
0292         goto free_drv;
0293     }
0294
0295     if (drv->data->get_version) {
0296         speedbin_nvmem = of_nvmem_cell_get(np, NULL);
0297         if (IS_ERR(speedbin_nvmem)) {
0298             if (PTR_ERR(speedbin_nvmem) != -EPROBE_DEFER)
0299                 dev_err(cpu_dev,
0300                     "Could not get nvmem cell: %ld\n",
0301                     PTR_ERR(speedbin_nvmem));
0302             ret = PTR_ERR(speedbin_nvmem);
0303             goto free_drv;
0304         }
0305
0306         ret = drv->data->get_version(cpu_dev,
0307                             speedbin_nvmem, &pvs_name, drv);
0308         if (ret) {
0309             nvmem_cell_put(speedbin_nvmem);
0310             goto free_drv;
0311         }
0312         nvmem_cell_put(speedbin_nvmem);
0313     }
0314     of_node_put(np);
0315
0316     drv->opp_tokens = kcalloc(num_possible_cpus(), sizeof(*drv->opp_tokens),
0317                   GFP_KERNEL);
0318     if (!drv->opp_tokens) {
0319         ret = -ENOMEM;
0320         goto free_drv;
0321     }
0322
0323     for_each_possible_cpu(cpu) {
0324         struct dev_pm_opp_config config = {
0325             .supported_hw = NULL,
0326         };
0327
0328         cpu_dev = get_cpu_device(cpu);
0329         if (NULL == cpu_dev) {
0330             ret = -ENODEV;
0331             goto free_opp;
0332         }
0333
0334         if (drv->data->get_version) {
0335             config.supported_hw = &drv->versions;
0336             config.supported_hw_count = 1;
0337
0338             if (pvs_name)
0339                 config.prop_name = pvs_name;
0340         }
0341
0342         if (drv->data->genpd_names) {
0343             config.genpd_names = drv->data->genpd_names;
0344             config.virt_devs = NULL;
0345         }
0346
0347         if (config.supported_hw || config.genpd_names) {
0348             drv->opp_tokens[cpu] = dev_pm_opp_set_config(cpu_dev, &config);
0349             if (drv->opp_tokens[cpu] < 0) {
0350                 ret = drv->opp_tokens[cpu];
0351                 dev_err(cpu_dev, "Failed to set OPP config\n");
0352                 goto free_opp;
0353             }
0354         }
0355     }
0356
0357     cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,
0358                               NULL, 0);
0359     if (!IS_ERR(cpufreq_dt_pdev)) {
0360         platform_set_drvdata(pdev, drv);
0361         return 0;
0362     }
0363
0364     ret = PTR_ERR(cpufreq_dt_pdev);
0365     dev_err(cpu_dev, "Failed to register platform device\n");
0366
0367 free_opp:
0368     for_each_possible_cpu(cpu)
0369         dev_pm_opp_clear_config(drv->opp_tokens[cpu]);
0370     kfree(drv->opp_tokens);
0371 free_drv:
0372     kfree(drv);
0373
0374     return ret;
0375 }
0376
0377 static int qcom_cpufreq_remove(struct platform_device *pdev)
0378 {
0379     struct qcom_cpufreq_drv *drv = platform_get_drvdata(pdev);
0380     unsigned int cpu;
0381
0382     platform_device_unregister(cpufreq_dt_pdev);
0383
0384     for_each_possible_cpu(cpu)
0385         dev_pm_opp_clear_config(drv->opp_tokens[cpu]);
0386
0387     kfree(drv->opp_tokens);
0388     kfree(drv);
0389
0390     return 0;
0391 }
0392
0393 static struct platform_driver qcom_cpufreq_driver = {
0394     .probe = qcom_cpufreq_probe,
0395     .remove = qcom_cpufreq_remove,
0396     .driver = {
0397         .name = "qcom-cpufreq-nvmem",
0398     },
0399 };
0400
0401 static const struct of_device_id qcom_cpufreq_match_list[] __initconst = {
0402     { .compatible = "qcom,apq8096", .data = &match_data_kryo },
0403     { .compatible = "qcom,msm8996", .data = &match_data_kryo },
0404     { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
0405     { .compatible = "qcom,ipq8064", .data = &match_data_krait },
0406     { .compatible = "qcom,apq8064", .data = &match_data_krait },
0407     { .compatible = "qcom,msm8974", .data = &match_data_krait },
0408     { .compatible = "qcom,msm8960", .data = &match_data_krait },
0409     {},
0410 };
0411 MODULE_DEVICE_TABLE(of, qcom_cpufreq_match_list);
0412
0413 /*
0414  * Since the driver depends on smem and nvmem drivers, which may
0415  * return EPROBE_DEFER, all the real activity is done in the probe,
0416  * which may be defered as well. The init here is only registering
0417  * the driver and the platform device.
0418  */
0419 static int __init qcom_cpufreq_init(void)
0420 {
0421     struct device_node *np = of_find_node_by_path("/");
0422     const struct of_device_id *match;
0423     int ret;
0424
0425     if (!np)
0426         return -ENODEV;
0427
0428     match = of_match_node(qcom_cpufreq_match_list, np);
0429     of_node_put(np);
0430     if (!match)
0431         return -ENODEV;
0432
0433     ret = platform_driver_register(&qcom_cpufreq_driver);
0434     if (unlikely(ret < 0))
0435         return ret;
0436
0437     cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem",
0438                              -1, match, sizeof(*match));
0439     ret = PTR_ERR_OR_ZERO(cpufreq_pdev);
0440     if (0 == ret)
0441         return 0;
0442
0443     platform_driver_unregister(&qcom_cpufreq_driver);
0444     return ret;
0445 }
0446 module_init(qcom_cpufreq_init);
0447
0448 static void __exit qcom_cpufreq_exit(void)
0449 {
0450     platform_device_unregister(cpufreq_pdev);
0451     platform_driver_unregister(&qcom_cpufreq_driver);
0452 }
0453 module_exit(qcom_cpufreq_exit);
0454
0455 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver");
0456 MODULE_LICENSE("GPL v2");