drivers/cpufreq/powernow-k8.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  (c) 2003-2006 Advanced Micro Devices, Inc.
0004  */
0005
0006 struct powernow_k8_data {
0007     unsigned int cpu;
0008
0009     u32 numps;  /* number of p-states */
0010     u32 batps;  /* number of p-states supported on battery */
0011
0012     /* these values are constant when the PSB is used to determine
0013      * vid/fid pairings, but are modified during the ->target() call
0014      * when ACPI is used */
0015     u32 rvo;     /* ramp voltage offset */
0016     u32 irt;     /* isochronous relief time */
0017     u32 vidmvs;  /* usable value calculated from mvs */
0018     u32 vstable; /* voltage stabilization time, units 20 us */
0019     u32 plllock; /* pll lock time, units 1 us */
0020     u32 exttype; /* extended interface = 1 */
0021
0022     /* keep track of the current fid / vid or pstate */
0023     u32 currvid;
0024     u32 currfid;
0025
0026     /* the powernow_table includes all frequency and vid/fid pairings:
0027      * fid are the lower 8 bits of the index, vid are the upper 8 bits.
0028      * frequency is in kHz */
0029     struct cpufreq_frequency_table  *powernow_table;
0030
0031     /* the acpi table needs to be kept. it's only available if ACPI was
0032      * used to determine valid frequency/vid/fid states */
0033     struct acpi_processor_performance acpi_data;
0034
0035     /* we need to keep track of associated cores, but let cpufreq
0036      * handle hotplug events - so just point at cpufreq pol->cpus
0037      * structure */
0038     struct cpumask *available_cores;
0039 };
0040
0041 /* processor's cpuid instruction support */
0042 #define CPUID_PROCESSOR_SIGNATURE   1   /* function 1 */
0043 #define CPUID_XFAM          0x0ff00000  /* extended family */
0044 #define CPUID_XFAM_K8           0
0045 #define CPUID_XMOD          0x000f0000  /* extended model */
0046 #define CPUID_XMOD_REV_MASK     0x000c0000
0047 #define CPUID_XFAM_10H          0x00100000  /* family 0x10 */
0048 #define CPUID_USE_XFAM_XMOD     0x00000f00
0049 #define CPUID_GET_MAX_CAPABILITIES  0x80000000
0050 #define CPUID_FREQ_VOLT_CAPABILITIES    0x80000007
0051 #define P_STATE_TRANSITION_CAPABLE  6
0052
0053 /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For     */
0054 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and   */
0055 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
0056 /* the register number is placed in ecx, and the data is returned in edx:eax. */
0057
0058 #define MSR_FIDVID_CTL      0xc0010041
0059 #define MSR_FIDVID_STATUS   0xc0010042
0060
0061 /* Field definitions within the FID VID Low Control MSR : */
0062 #define MSR_C_LO_INIT_FID_VID     0x00010000
0063 #define MSR_C_LO_NEW_VID          0x00003f00
0064 #define MSR_C_LO_NEW_FID          0x0000003f
0065 #define MSR_C_LO_VID_SHIFT        8
0066
0067 /* Field definitions within the FID VID High Control MSR : */
0068 #define MSR_C_HI_STP_GNT_TO   0x000fffff
0069
0070 /* Field definitions within the FID VID Low Status MSR : */
0071 #define MSR_S_LO_CHANGE_PENDING   0x80000000   /* cleared when completed */
0072 #define MSR_S_LO_MAX_RAMP_VID     0x3f000000
0073 #define MSR_S_LO_MAX_FID          0x003f0000
0074 #define MSR_S_LO_START_FID        0x00003f00
0075 #define MSR_S_LO_CURRENT_FID      0x0000003f
0076
0077 /* Field definitions within the FID VID High Status MSR : */
0078 #define MSR_S_HI_MIN_WORKING_VID  0x3f000000
0079 #define MSR_S_HI_MAX_WORKING_VID  0x003f0000
0080 #define MSR_S_HI_START_VID        0x00003f00
0081 #define MSR_S_HI_CURRENT_VID      0x0000003f
0082 #define MSR_C_HI_STP_GNT_BENIGN   0x00000001
0083
0084 /*
0085  * There are restrictions frequencies have to follow:
0086  * - only 1 entry in the low fid table ( <=1.4GHz )
0087  * - lowest entry in the high fid table must be >= 2 * the entry in the
0088  *   low fid table
0089  * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
0090  *   in the low fid table
0091  * - the parts can only step at <= 200 MHz intervals, odd fid values are
0092  *   supported in revision G and later revisions.
0093  * - lowest frequency must be >= interprocessor hypertransport link speed
0094  *   (only applies to MP systems obviously)
0095  */
0096
0097 /* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
0098 #define LO_FID_TABLE_TOP     7  /* fid values marking the boundary    */
0099 #define HI_FID_TABLE_BOTTOM  8  /* between the low and high tables    */
0100
0101 #define LO_VCOFREQ_TABLE_TOP    1400    /* corresponding vco frequency values */
0102 #define HI_VCOFREQ_TABLE_BOTTOM 1600
0103
0104 #define MIN_FREQ_RESOLUTION  200 /* fids jump by 2 matching freq jumps by 200 */
0105
0106 #define MAX_FID 0x2a    /* Spec only gives FID values as far as 5 GHz */
0107 #define LEAST_VID 0x3e  /* Lowest (numerically highest) useful vid value */
0108
0109 #define MIN_FREQ 800    /* Min and max freqs, per spec */
0110 #define MAX_FREQ 5000
0111
0112 #define INVALID_FID_MASK 0xffffffc0  /* not a valid fid if these bits are set */
0113 #define INVALID_VID_MASK 0xffffffc0  /* not a valid vid if these bits are set */
0114
0115 #define VID_OFF 0x3f
0116
0117 #define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */
0118
0119 #define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */
0120
0121 #define MAXIMUM_VID_STEPS 1  /* Current cpus only allow a single step of 25mV */
0122 #define VST_UNITS_20US 20   /* Voltage Stabilization Time is in units of 20us */
0123
0124 /*
0125  * Most values of interest are encoded in a single field of the _PSS
0126  * entries: the "control" value.
0127  */
0128
0129 #define IRT_SHIFT      30
0130 #define RVO_SHIFT      28
0131 #define EXT_TYPE_SHIFT 27
0132 #define PLL_L_SHIFT    20
0133 #define MVS_SHIFT      18
0134 #define VST_SHIFT      11
0135 #define VID_SHIFT       6
0136 #define IRT_MASK        3
0137 #define RVO_MASK        3
0138 #define EXT_TYPE_MASK   1
0139 #define PLL_L_MASK   0x7f
0140 #define MVS_MASK        3
0141 #define VST_MASK     0x7f
0142 #define VID_MASK     0x1f
0143 #define FID_MASK     0x1f
0144 #define EXT_VID_MASK 0x3f
0145 #define EXT_FID_MASK 0x3f
0146
0147
0148 /*
0149  * Version 1.4 of the PSB table. This table is constructed by BIOS and is
0150  * to tell the OS's power management driver which VIDs and FIDs are
0151  * supported by this particular processor.
0152  * If the data in the PSB / PST is wrong, then this driver will program the
0153  * wrong values into hardware, which is very likely to lead to a crash.
0154  */
0155
0156 #define PSB_ID_STRING      "AMDK7PNOW!"
0157 #define PSB_ID_STRING_LEN  10
0158
0159 #define PSB_VERSION_1_4  0x14
0160
0161 struct psb_s {
0162     u8 signature[10];
0163     u8 tableversion;
0164     u8 flags1;
0165     u16 vstable;
0166     u8 flags2;
0167     u8 num_tables;
0168     u32 cpuid;
0169     u8 plllocktime;
0170     u8 maxfid;
0171     u8 maxvid;
0172     u8 numps;
0173 };
0174
0175 /* Pairs of fid/vid values are appended to the version 1.4 PSB table. */
0176 struct pst_s {
0177     u8 fid;
0178     u8 vid;
0179 };
0180
0181 static int core_voltage_pre_transition(struct powernow_k8_data *data,
0182     u32 reqvid, u32 regfid);
0183 static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid);
0184 static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid);
0185
0186 static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index);
0187
0188 static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);