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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
0004  *  and                       Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
0005  *
0006  * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
0007  * that is iMac G5 and latest single CPU desktop.
0008  */
0009 
0010 #undef DEBUG
0011 
0012 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0013 
0014 #include <linux/module.h>
0015 #include <linux/types.h>
0016 #include <linux/errno.h>
0017 #include <linux/kernel.h>
0018 #include <linux/delay.h>
0019 #include <linux/sched.h>
0020 #include <linux/cpufreq.h>
0021 #include <linux/init.h>
0022 #include <linux/completion.h>
0023 #include <linux/mutex.h>
0024 #include <linux/of_device.h>
0025 
0026 #include <asm/machdep.h>
0027 #include <asm/irq.h>
0028 #include <asm/sections.h>
0029 #include <asm/cputable.h>
0030 #include <asm/time.h>
0031 #include <asm/smu.h>
0032 #include <asm/pmac_pfunc.h>
0033 
0034 #define DBG(fmt...) pr_debug(fmt)
0035 
0036 /* see 970FX user manual */
0037 
0038 #define SCOM_PCR 0x0aa001           /* PCR scom addr */
0039 
0040 #define PCR_HILO_SELECT     0x80000000U /* 1 = PCR, 0 = PCRH */
0041 #define PCR_SPEED_FULL      0x00000000U /* 1:1 speed value */
0042 #define PCR_SPEED_HALF      0x00020000U /* 1:2 speed value */
0043 #define PCR_SPEED_QUARTER   0x00040000U /* 1:4 speed value */
0044 #define PCR_SPEED_MASK      0x000e0000U /* speed mask */
0045 #define PCR_SPEED_SHIFT     17
0046 #define PCR_FREQ_REQ_VALID  0x00010000U /* freq request valid */
0047 #define PCR_VOLT_REQ_VALID  0x00008000U /* volt request valid */
0048 #define PCR_TARGET_TIME_MASK    0x00006000U /* target time */
0049 #define PCR_STATLAT_MASK    0x00001f00U /* STATLAT value */
0050 #define PCR_SNOOPLAT_MASK   0x000000f0U /* SNOOPLAT value */
0051 #define PCR_SNOOPACC_MASK   0x0000000fU /* SNOOPACC value */
0052 
0053 #define SCOM_PSR 0x408001           /* PSR scom addr */
0054 /* warning: PSR is a 64 bits register */
0055 #define PSR_CMD_RECEIVED    0x2000000000000000U   /* command received */
0056 #define PSR_CMD_COMPLETED   0x1000000000000000U   /* command completed */
0057 #define PSR_CUR_SPEED_MASK  0x0300000000000000U   /* current speed */
0058 #define PSR_CUR_SPEED_SHIFT (56)
0059 
0060 /*
0061  * The G5 only supports two frequencies (Quarter speed is not supported)
0062  */
0063 #define CPUFREQ_HIGH                  0
0064 #define CPUFREQ_LOW                   1
0065 
0066 static struct cpufreq_frequency_table g5_cpu_freqs[] = {
0067     {0, CPUFREQ_HIGH,   0},
0068     {0, CPUFREQ_LOW,    0},
0069     {0, 0,          CPUFREQ_TABLE_END},
0070 };
0071 
0072 /* Power mode data is an array of the 32 bits PCR values to use for
0073  * the various frequencies, retrieved from the device-tree
0074  */
0075 static int g5_pmode_cur;
0076 
0077 static void (*g5_switch_volt)(int speed_mode);
0078 static int (*g5_switch_freq)(int speed_mode);
0079 static int (*g5_query_freq)(void);
0080 
0081 static unsigned long transition_latency;
0082 
0083 #ifdef CONFIG_PMAC_SMU
0084 
0085 static const u32 *g5_pmode_data;
0086 static int g5_pmode_max;
0087 
0088 static struct smu_sdbp_fvt *g5_fvt_table;   /* table of op. points */
0089 static int g5_fvt_count;            /* number of op. points */
0090 static int g5_fvt_cur;              /* current op. point */
0091 
0092 /*
0093  * SMU based voltage switching for Neo2 platforms
0094  */
0095 
0096 static void g5_smu_switch_volt(int speed_mode)
0097 {
0098     struct smu_simple_cmd   cmd;
0099 
0100     DECLARE_COMPLETION_ONSTACK(comp);
0101     smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
0102              &comp, 'V', 'S', 'L', 'E', 'W',
0103              0xff, g5_fvt_cur+1, speed_mode);
0104     wait_for_completion(&comp);
0105 }
0106 
0107 /*
0108  * Platform function based voltage/vdnap switching for Neo2
0109  */
0110 
0111 static struct pmf_function *pfunc_set_vdnap0;
0112 static struct pmf_function *pfunc_vdnap0_complete;
0113 
0114 static void g5_vdnap_switch_volt(int speed_mode)
0115 {
0116     struct pmf_args args;
0117     u32 slew, done = 0;
0118     unsigned long timeout;
0119 
0120     slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0;
0121     args.count = 1;
0122     args.u[0].p = &slew;
0123 
0124     pmf_call_one(pfunc_set_vdnap0, &args);
0125 
0126     /* It's an irq GPIO so we should be able to just block here,
0127      * I'll do that later after I've properly tested the IRQ code for
0128      * platform functions
0129      */
0130     timeout = jiffies + HZ/10;
0131     while(!time_after(jiffies, timeout)) {
0132         args.count = 1;
0133         args.u[0].p = &done;
0134         pmf_call_one(pfunc_vdnap0_complete, &args);
0135         if (done)
0136             break;
0137         usleep_range(1000, 1000);
0138     }
0139     if (done == 0)
0140         pr_warn("Timeout in clock slewing !\n");
0141 }
0142 
0143 
0144 /*
0145  * SCOM based frequency switching for 970FX rev3
0146  */
0147 static int g5_scom_switch_freq(int speed_mode)
0148 {
0149     unsigned long flags;
0150     int to;
0151 
0152     /* If frequency is going up, first ramp up the voltage */
0153     if (speed_mode < g5_pmode_cur)
0154         g5_switch_volt(speed_mode);
0155 
0156     local_irq_save(flags);
0157 
0158     /* Clear PCR high */
0159     scom970_write(SCOM_PCR, 0);
0160     /* Clear PCR low */
0161         scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
0162     /* Set PCR low */
0163     scom970_write(SCOM_PCR, PCR_HILO_SELECT |
0164               g5_pmode_data[speed_mode]);
0165 
0166     /* Wait for completion */
0167     for (to = 0; to < 10; to++) {
0168         unsigned long psr = scom970_read(SCOM_PSR);
0169 
0170         if ((psr & PSR_CMD_RECEIVED) == 0 &&
0171             (((psr >> PSR_CUR_SPEED_SHIFT) ^
0172               (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
0173             == 0)
0174             break;
0175         if (psr & PSR_CMD_COMPLETED)
0176             break;
0177         udelay(100);
0178     }
0179 
0180     local_irq_restore(flags);
0181 
0182     /* If frequency is going down, last ramp the voltage */
0183     if (speed_mode > g5_pmode_cur)
0184         g5_switch_volt(speed_mode);
0185 
0186     g5_pmode_cur = speed_mode;
0187     ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
0188 
0189     return 0;
0190 }
0191 
0192 static int g5_scom_query_freq(void)
0193 {
0194     unsigned long psr = scom970_read(SCOM_PSR);
0195     int i;
0196 
0197     for (i = 0; i <= g5_pmode_max; i++)
0198         if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
0199               (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
0200             break;
0201     return i;
0202 }
0203 
0204 /*
0205  * Fake voltage switching for platforms with missing support
0206  */
0207 
0208 static void g5_dummy_switch_volt(int speed_mode)
0209 {
0210 }
0211 
0212 #endif /* CONFIG_PMAC_SMU */
0213 
0214 /*
0215  * Platform function based voltage switching for PowerMac7,2 & 7,3
0216  */
0217 
0218 static struct pmf_function *pfunc_cpu0_volt_high;
0219 static struct pmf_function *pfunc_cpu0_volt_low;
0220 static struct pmf_function *pfunc_cpu1_volt_high;
0221 static struct pmf_function *pfunc_cpu1_volt_low;
0222 
0223 static void g5_pfunc_switch_volt(int speed_mode)
0224 {
0225     if (speed_mode == CPUFREQ_HIGH) {
0226         if (pfunc_cpu0_volt_high)
0227             pmf_call_one(pfunc_cpu0_volt_high, NULL);
0228         if (pfunc_cpu1_volt_high)
0229             pmf_call_one(pfunc_cpu1_volt_high, NULL);
0230     } else {
0231         if (pfunc_cpu0_volt_low)
0232             pmf_call_one(pfunc_cpu0_volt_low, NULL);
0233         if (pfunc_cpu1_volt_low)
0234             pmf_call_one(pfunc_cpu1_volt_low, NULL);
0235     }
0236     usleep_range(10000, 10000); /* should be faster , to fix */
0237 }
0238 
0239 /*
0240  * Platform function based frequency switching for PowerMac7,2 & 7,3
0241  */
0242 
0243 static struct pmf_function *pfunc_cpu_setfreq_high;
0244 static struct pmf_function *pfunc_cpu_setfreq_low;
0245 static struct pmf_function *pfunc_cpu_getfreq;
0246 static struct pmf_function *pfunc_slewing_done;
0247 
0248 static int g5_pfunc_switch_freq(int speed_mode)
0249 {
0250     struct pmf_args args;
0251     u32 done = 0;
0252     unsigned long timeout;
0253     int rc;
0254 
0255     DBG("g5_pfunc_switch_freq(%d)\n", speed_mode);
0256 
0257     /* If frequency is going up, first ramp up the voltage */
0258     if (speed_mode < g5_pmode_cur)
0259         g5_switch_volt(speed_mode);
0260 
0261     /* Do it */
0262     if (speed_mode == CPUFREQ_HIGH)
0263         rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL);
0264     else
0265         rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL);
0266 
0267     if (rc)
0268         pr_warn("pfunc switch error %d\n", rc);
0269 
0270     /* It's an irq GPIO so we should be able to just block here,
0271      * I'll do that later after I've properly tested the IRQ code for
0272      * platform functions
0273      */
0274     timeout = jiffies + HZ/10;
0275     while(!time_after(jiffies, timeout)) {
0276         args.count = 1;
0277         args.u[0].p = &done;
0278         pmf_call_one(pfunc_slewing_done, &args);
0279         if (done)
0280             break;
0281         usleep_range(500, 500);
0282     }
0283     if (done == 0)
0284         pr_warn("Timeout in clock slewing !\n");
0285 
0286     /* If frequency is going down, last ramp the voltage */
0287     if (speed_mode > g5_pmode_cur)
0288         g5_switch_volt(speed_mode);
0289 
0290     g5_pmode_cur = speed_mode;
0291     ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
0292 
0293     return 0;
0294 }
0295 
0296 static int g5_pfunc_query_freq(void)
0297 {
0298     struct pmf_args args;
0299     u32 val = 0;
0300 
0301     args.count = 1;
0302     args.u[0].p = &val;
0303     pmf_call_one(pfunc_cpu_getfreq, &args);
0304     return val ? CPUFREQ_HIGH : CPUFREQ_LOW;
0305 }
0306 
0307 
0308 /*
0309  * Common interface to the cpufreq core
0310  */
0311 
0312 static int g5_cpufreq_target(struct cpufreq_policy *policy, unsigned int index)
0313 {
0314     return g5_switch_freq(index);
0315 }
0316 
0317 static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
0318 {
0319     return g5_cpu_freqs[g5_pmode_cur].frequency;
0320 }
0321 
0322 static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
0323 {
0324     cpufreq_generic_init(policy, g5_cpu_freqs, transition_latency);
0325     return 0;
0326 }
0327 
0328 static struct cpufreq_driver g5_cpufreq_driver = {
0329     .name       = "powermac",
0330     .flags      = CPUFREQ_CONST_LOOPS,
0331     .init       = g5_cpufreq_cpu_init,
0332     .verify     = cpufreq_generic_frequency_table_verify,
0333     .target_index   = g5_cpufreq_target,
0334     .get        = g5_cpufreq_get_speed,
0335     .attr       = cpufreq_generic_attr,
0336 };
0337 
0338 
0339 #ifdef CONFIG_PMAC_SMU
0340 
0341 static int __init g5_neo2_cpufreq_init(struct device_node *cpunode)
0342 {
0343     unsigned int psize, ssize;
0344     unsigned long max_freq;
0345     char *freq_method, *volt_method;
0346     const u32 *valp;
0347     u32 pvr_hi;
0348     int use_volts_vdnap = 0;
0349     int use_volts_smu = 0;
0350     int rc = -ENODEV;
0351 
0352     /* Check supported platforms */
0353     if (of_machine_is_compatible("PowerMac8,1") ||
0354         of_machine_is_compatible("PowerMac8,2") ||
0355         of_machine_is_compatible("PowerMac9,1") ||
0356         of_machine_is_compatible("PowerMac12,1"))
0357         use_volts_smu = 1;
0358     else if (of_machine_is_compatible("PowerMac11,2"))
0359         use_volts_vdnap = 1;
0360     else
0361         return -ENODEV;
0362 
0363     /* Check 970FX for now */
0364     valp = of_get_property(cpunode, "cpu-version", NULL);
0365     if (!valp) {
0366         DBG("No cpu-version property !\n");
0367         goto bail_noprops;
0368     }
0369     pvr_hi = (*valp) >> 16;
0370     if (pvr_hi != 0x3c && pvr_hi != 0x44) {
0371         pr_err("Unsupported CPU version\n");
0372         goto bail_noprops;
0373     }
0374 
0375     /* Look for the powertune data in the device-tree */
0376     g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize);
0377     if (!g5_pmode_data) {
0378         DBG("No power-mode-data !\n");
0379         goto bail_noprops;
0380     }
0381     g5_pmode_max = psize / sizeof(u32) - 1;
0382 
0383     if (use_volts_smu) {
0384         const struct smu_sdbp_header *shdr;
0385 
0386         /* Look for the FVT table */
0387         shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
0388         if (!shdr)
0389             goto bail_noprops;
0390         g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
0391         ssize = (shdr->len * sizeof(u32)) - sizeof(*shdr);
0392         g5_fvt_count = ssize / sizeof(*g5_fvt_table);
0393         g5_fvt_cur = 0;
0394 
0395         /* Sanity checking */
0396         if (g5_fvt_count < 1 || g5_pmode_max < 1)
0397             goto bail_noprops;
0398 
0399         g5_switch_volt = g5_smu_switch_volt;
0400         volt_method = "SMU";
0401     } else if (use_volts_vdnap) {
0402         struct device_node *root;
0403 
0404         root = of_find_node_by_path("/");
0405         if (root == NULL) {
0406             pr_err("Can't find root of device tree\n");
0407             goto bail_noprops;
0408         }
0409         pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0");
0410         pfunc_vdnap0_complete =
0411             pmf_find_function(root, "slewing-done");
0412         of_node_put(root);
0413         if (pfunc_set_vdnap0 == NULL ||
0414             pfunc_vdnap0_complete == NULL) {
0415             pr_err("Can't find required platform function\n");
0416             goto bail_noprops;
0417         }
0418 
0419         g5_switch_volt = g5_vdnap_switch_volt;
0420         volt_method = "GPIO";
0421     } else {
0422         g5_switch_volt = g5_dummy_switch_volt;
0423         volt_method = "none";
0424     }
0425 
0426     /*
0427      * From what I see, clock-frequency is always the maximal frequency.
0428      * The current driver can not slew sysclk yet, so we really only deal
0429      * with powertune steps for now. We also only implement full freq and
0430      * half freq in this version. So far, I haven't yet seen a machine
0431      * supporting anything else.
0432      */
0433     valp = of_get_property(cpunode, "clock-frequency", NULL);
0434     if (!valp)
0435         return -ENODEV;
0436     max_freq = (*valp)/1000;
0437     g5_cpu_freqs[0].frequency = max_freq;
0438     g5_cpu_freqs[1].frequency = max_freq/2;
0439 
0440     /* Set callbacks */
0441     transition_latency = 12000;
0442     g5_switch_freq = g5_scom_switch_freq;
0443     g5_query_freq = g5_scom_query_freq;
0444     freq_method = "SCOM";
0445 
0446     /* Force apply current frequency to make sure everything is in
0447      * sync (voltage is right for example). Firmware may leave us with
0448      * a strange setting ...
0449      */
0450     g5_switch_volt(CPUFREQ_HIGH);
0451     msleep(10);
0452     g5_pmode_cur = -1;
0453     g5_switch_freq(g5_query_freq());
0454 
0455     pr_info("Registering G5 CPU frequency driver\n");
0456     pr_info("Frequency method: %s, Voltage method: %s\n",
0457         freq_method, volt_method);
0458     pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
0459         g5_cpu_freqs[1].frequency/1000,
0460         g5_cpu_freqs[0].frequency/1000,
0461         g5_cpu_freqs[g5_pmode_cur].frequency/1000);
0462 
0463     rc = cpufreq_register_driver(&g5_cpufreq_driver);
0464 
0465     /* We keep the CPU node on hold... hopefully, Apple G5 don't have
0466      * hotplug CPU with a dynamic device-tree ...
0467      */
0468     return rc;
0469 
0470  bail_noprops:
0471     of_node_put(cpunode);
0472 
0473     return rc;
0474 }
0475 
0476 #endif /* CONFIG_PMAC_SMU */
0477 
0478 
0479 static int __init g5_pm72_cpufreq_init(struct device_node *cpunode)
0480 {
0481     struct device_node *cpuid = NULL, *hwclock = NULL;
0482     const u8 *eeprom = NULL;
0483     const u32 *valp;
0484     u64 max_freq, min_freq, ih, il;
0485     int has_volt = 1, rc = 0;
0486 
0487     DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and"
0488         " RackMac3,1...\n");
0489 
0490     /* Lookup the cpuid eeprom node */
0491         cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0");
0492     if (cpuid != NULL)
0493         eeprom = of_get_property(cpuid, "cpuid", NULL);
0494     if (eeprom == NULL) {
0495         pr_err("Can't find cpuid EEPROM !\n");
0496         rc = -ENODEV;
0497         goto bail;
0498     }
0499 
0500     /* Lookup the i2c hwclock */
0501     for_each_node_by_name(hwclock, "i2c-hwclock") {
0502         const char *loc = of_get_property(hwclock,
0503                 "hwctrl-location", NULL);
0504         if (loc == NULL)
0505             continue;
0506         if (strcmp(loc, "CPU CLOCK"))
0507             continue;
0508         if (!of_get_property(hwclock, "platform-get-frequency", NULL))
0509             continue;
0510         break;
0511     }
0512     if (hwclock == NULL) {
0513         pr_err("Can't find i2c clock chip !\n");
0514         rc = -ENODEV;
0515         goto bail;
0516     }
0517 
0518     DBG("cpufreq: i2c clock chip found: %pOF\n", hwclock);
0519 
0520     /* Now get all the platform functions */
0521     pfunc_cpu_getfreq =
0522         pmf_find_function(hwclock, "get-frequency");
0523     pfunc_cpu_setfreq_high =
0524         pmf_find_function(hwclock, "set-frequency-high");
0525     pfunc_cpu_setfreq_low =
0526         pmf_find_function(hwclock, "set-frequency-low");
0527     pfunc_slewing_done =
0528         pmf_find_function(hwclock, "slewing-done");
0529     pfunc_cpu0_volt_high =
0530         pmf_find_function(hwclock, "set-voltage-high-0");
0531     pfunc_cpu0_volt_low =
0532         pmf_find_function(hwclock, "set-voltage-low-0");
0533     pfunc_cpu1_volt_high =
0534         pmf_find_function(hwclock, "set-voltage-high-1");
0535     pfunc_cpu1_volt_low =
0536         pmf_find_function(hwclock, "set-voltage-low-1");
0537 
0538     /* Check we have minimum requirements */
0539     if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL ||
0540         pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) {
0541         pr_err("Can't find platform functions !\n");
0542         rc = -ENODEV;
0543         goto bail;
0544     }
0545 
0546     /* Check that we have complete sets */
0547     if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) {
0548         pmf_put_function(pfunc_cpu0_volt_high);
0549         pmf_put_function(pfunc_cpu0_volt_low);
0550         pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL;
0551         has_volt = 0;
0552     }
0553     if (!has_volt ||
0554         pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) {
0555         pmf_put_function(pfunc_cpu1_volt_high);
0556         pmf_put_function(pfunc_cpu1_volt_low);
0557         pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL;
0558     }
0559 
0560     /* Note: The device tree also contains a "platform-set-values"
0561      * function for which I haven't quite figured out the usage. It
0562      * might have to be called on init and/or wakeup, I'm not too sure
0563      * but things seem to work fine without it so far ...
0564      */
0565 
0566     /* Get max frequency from device-tree */
0567     valp = of_get_property(cpunode, "clock-frequency", NULL);
0568     if (!valp) {
0569         pr_err("Can't find CPU frequency !\n");
0570         rc = -ENODEV;
0571         goto bail;
0572     }
0573 
0574     max_freq = (*valp)/1000;
0575 
0576     /* Now calculate reduced frequency by using the cpuid input freq
0577      * ratio. This requires 64 bits math unless we are willing to lose
0578      * some precision
0579      */
0580     ih = *((u32 *)(eeprom + 0x10));
0581     il = *((u32 *)(eeprom + 0x20));
0582 
0583     /* Check for machines with no useful settings */
0584     if (il == ih) {
0585         pr_warn("No low frequency mode available on this model !\n");
0586         rc = -ENODEV;
0587         goto bail;
0588     }
0589 
0590     min_freq = 0;
0591     if (ih != 0 && il != 0)
0592         min_freq = (max_freq * il) / ih;
0593 
0594     /* Sanity check */
0595     if (min_freq >= max_freq || min_freq < 1000) {
0596         pr_err("Can't calculate low frequency !\n");
0597         rc = -ENXIO;
0598         goto bail;
0599     }
0600     g5_cpu_freqs[0].frequency = max_freq;
0601     g5_cpu_freqs[1].frequency = min_freq;
0602 
0603     /* Based on a measurement on Xserve G5, rounded up. */
0604     transition_latency = 10 * NSEC_PER_MSEC;
0605 
0606     /* Set callbacks */
0607     g5_switch_volt = g5_pfunc_switch_volt;
0608     g5_switch_freq = g5_pfunc_switch_freq;
0609     g5_query_freq = g5_pfunc_query_freq;
0610 
0611     /* Force apply current frequency to make sure everything is in
0612      * sync (voltage is right for example). Firmware may leave us with
0613      * a strange setting ...
0614      */
0615     g5_switch_volt(CPUFREQ_HIGH);
0616     msleep(10);
0617     g5_pmode_cur = -1;
0618     g5_switch_freq(g5_query_freq());
0619 
0620     pr_info("Registering G5 CPU frequency driver\n");
0621     pr_info("Frequency method: i2c/pfunc, Voltage method: %s\n",
0622         has_volt ? "i2c/pfunc" : "none");
0623     pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
0624         g5_cpu_freqs[1].frequency/1000,
0625         g5_cpu_freqs[0].frequency/1000,
0626         g5_cpu_freqs[g5_pmode_cur].frequency/1000);
0627 
0628     rc = cpufreq_register_driver(&g5_cpufreq_driver);
0629  bail:
0630     if (rc != 0) {
0631         pmf_put_function(pfunc_cpu_getfreq);
0632         pmf_put_function(pfunc_cpu_setfreq_high);
0633         pmf_put_function(pfunc_cpu_setfreq_low);
0634         pmf_put_function(pfunc_slewing_done);
0635         pmf_put_function(pfunc_cpu0_volt_high);
0636         pmf_put_function(pfunc_cpu0_volt_low);
0637         pmf_put_function(pfunc_cpu1_volt_high);
0638         pmf_put_function(pfunc_cpu1_volt_low);
0639     }
0640     of_node_put(hwclock);
0641     of_node_put(cpuid);
0642     of_node_put(cpunode);
0643 
0644     return rc;
0645 }
0646 
0647 static int __init g5_cpufreq_init(void)
0648 {
0649     struct device_node *cpunode;
0650     int rc = 0;
0651 
0652     /* Get first CPU node */
0653     cpunode = of_cpu_device_node_get(0);
0654     if (cpunode == NULL) {
0655         pr_err("Can't find any CPU node\n");
0656         return -ENODEV;
0657     }
0658 
0659     if (of_machine_is_compatible("PowerMac7,2") ||
0660         of_machine_is_compatible("PowerMac7,3") ||
0661         of_machine_is_compatible("RackMac3,1"))
0662         rc = g5_pm72_cpufreq_init(cpunode);
0663 #ifdef CONFIG_PMAC_SMU
0664     else
0665         rc = g5_neo2_cpufreq_init(cpunode);
0666 #endif /* CONFIG_PMAC_SMU */
0667 
0668     return rc;
0669 }
0670 
0671 module_init(g5_cpufreq_init);
0672 
0673 
0674 MODULE_LICENSE("GPL");
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