drivers/cpufreq/p4-clockmod.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Pentium 4/Xeon CPU on demand clock modulation/speed scaling
0004  *  (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
0005  *  (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com>
0006  *  (C) 2002 Arjan van de Ven <arjanv@redhat.com>
0007  *  (C) 2002 Tora T. Engstad
0008  *  All Rights Reserved
0009  *
0010  *      The author(s) of this software shall not be held liable for damages
0011  *      of any nature resulting due to the use of this software. This
0012  *      software is provided AS-IS with no warranties.
0013  *
0014  *  Date        Errata          Description
0015  *  20020525    N44, O17    12.5% or 25% DC causes lockup
0016  */
0017
0018 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0019
0020 #include <linux/kernel.h>
0021 #include <linux/module.h>
0022 #include <linux/init.h>
0023 #include <linux/smp.h>
0024 #include <linux/cpufreq.h>
0025 #include <linux/cpumask.h>
0026 #include <linux/timex.h>
0027
0028 #include <asm/processor.h>
0029 #include <asm/msr.h>
0030 #include <asm/timer.h>
0031 #include <asm/cpu_device_id.h>
0032
0033 #include "speedstep-lib.h"
0034
0035 /*
0036  * Duty Cycle (3bits), note DC_DISABLE is not specified in
0037  * intel docs i just use it to mean disable
0038  */
0039 enum {
0040     DC_RESV, DC_DFLT, DC_25PT, DC_38PT, DC_50PT,
0041     DC_64PT, DC_75PT, DC_88PT, DC_DISABLE
0042 };
0043
0044 #define DC_ENTRIES  8
0045
0046
0047 static int has_N44_O17_errata[NR_CPUS];
0048 static unsigned int stock_freq;
0049 static struct cpufreq_driver p4clockmod_driver;
0050 static unsigned int cpufreq_p4_get(unsigned int cpu);
0051
0052 static int cpufreq_p4_setdc(unsigned int cpu, unsigned int newstate)
0053 {
0054     u32 l, h;
0055
0056     if ((newstate > DC_DISABLE) || (newstate == DC_RESV))
0057         return -EINVAL;
0058
0059     rdmsr_on_cpu(cpu, MSR_IA32_THERM_STATUS, &l, &h);
0060
0061     if (l & 0x01)
0062         pr_debug("CPU#%d currently thermal throttled\n", cpu);
0063
0064     if (has_N44_O17_errata[cpu] &&
0065         (newstate == DC_25PT || newstate == DC_DFLT))
0066         newstate = DC_38PT;
0067
0068     rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h);
0069     if (newstate == DC_DISABLE) {
0070         pr_debug("CPU#%d disabling modulation\n", cpu);
0071         wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l & ~(1<<4), h);
0072     } else {
0073         pr_debug("CPU#%d setting duty cycle to %d%%\n",
0074             cpu, ((125 * newstate) / 10));
0075         /* bits 63 - 5  : reserved
0076          * bit  4   : enable/disable
0077          * bits 3-1 : duty cycle
0078          * bit  0   : reserved
0079          */
0080         l = (l & ~14);
0081         l = l | (1<<4) | ((newstate & 0x7)<<1);
0082         wrmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, l, h);
0083     }
0084
0085     return 0;
0086 }
0087
0088
0089 static struct cpufreq_frequency_table p4clockmod_table[] = {
0090     {0, DC_RESV, CPUFREQ_ENTRY_INVALID},
0091     {0, DC_DFLT, 0},
0092     {0, DC_25PT, 0},
0093     {0, DC_38PT, 0},
0094     {0, DC_50PT, 0},
0095     {0, DC_64PT, 0},
0096     {0, DC_75PT, 0},
0097     {0, DC_88PT, 0},
0098     {0, DC_DISABLE, 0},
0099     {0, DC_RESV, CPUFREQ_TABLE_END},
0100 };
0101
0102
0103 static int cpufreq_p4_target(struct cpufreq_policy *policy, unsigned int index)
0104 {
0105     int i;
0106
0107     /* run on each logical CPU,
0108      * see section 13.15.3 of IA32 Intel Architecture Software
0109      * Developer's Manual, Volume 3
0110      */
0111     for_each_cpu(i, policy->cpus)
0112         cpufreq_p4_setdc(i, p4clockmod_table[index].driver_data);
0113
0114     return 0;
0115 }
0116
0117
0118 static unsigned int cpufreq_p4_get_frequency(struct cpuinfo_x86 *c)
0119 {
0120     if (c->x86 == 0x06) {
0121         if (cpu_has(c, X86_FEATURE_EST))
0122             pr_warn_once("Warning: EST-capable CPU detected. The acpi-cpufreq module offers voltage scaling in addition to frequency scaling. You should use that instead of p4-clockmod, if possible.\n");
0123         switch (c->x86_model) {
0124         case 0x0E: /* Core */
0125         case 0x0F: /* Core Duo */
0126         case 0x16: /* Celeron Core */
0127         case 0x1C: /* Atom */
0128             p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
0129             return speedstep_get_frequency(SPEEDSTEP_CPU_PCORE);
0130         case 0x0D: /* Pentium M (Dothan) */
0131             p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
0132             fallthrough;
0133         case 0x09: /* Pentium M (Banias) */
0134             return speedstep_get_frequency(SPEEDSTEP_CPU_PM);
0135         }
0136     }
0137
0138     if (c->x86 != 0xF)
0139         return 0;
0140
0141     /* on P-4s, the TSC runs with constant frequency independent whether
0142      * throttling is active or not. */
0143     p4clockmod_driver.flags |= CPUFREQ_CONST_LOOPS;
0144
0145     if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4M) {
0146         pr_warn("Warning: Pentium 4-M detected. The speedstep-ich or acpi cpufreq modules offer voltage scaling in addition of frequency scaling. You should use either one instead of p4-clockmod, if possible.\n");
0147         return speedstep_get_frequency(SPEEDSTEP_CPU_P4M);
0148     }
0149
0150     return speedstep_get_frequency(SPEEDSTEP_CPU_P4D);
0151 }
0152
0153
0154
0155 static int cpufreq_p4_cpu_init(struct cpufreq_policy *policy)
0156 {
0157     struct cpuinfo_x86 *c = &cpu_data(policy->cpu);
0158     int cpuid = 0;
0159     unsigned int i;
0160
0161 #ifdef CONFIG_SMP
0162     cpumask_copy(policy->cpus, topology_sibling_cpumask(policy->cpu));
0163 #endif
0164
0165     /* Errata workaround */
0166     cpuid = (c->x86 << 8) | (c->x86_model << 4) | c->x86_stepping;
0167     switch (cpuid) {
0168     case 0x0f07:
0169     case 0x0f0a:
0170     case 0x0f11:
0171     case 0x0f12:
0172         has_N44_O17_errata[policy->cpu] = 1;
0173         pr_debug("has errata -- disabling low frequencies\n");
0174     }
0175
0176     if (speedstep_detect_processor() == SPEEDSTEP_CPU_P4D &&
0177         c->x86_model < 2) {
0178         /* switch to maximum frequency and measure result */
0179         cpufreq_p4_setdc(policy->cpu, DC_DISABLE);
0180         recalibrate_cpu_khz();
0181     }
0182     /* get max frequency */
0183     stock_freq = cpufreq_p4_get_frequency(c);
0184     if (!stock_freq)
0185         return -EINVAL;
0186
0187     /* table init */
0188     for (i = 1; (p4clockmod_table[i].frequency != CPUFREQ_TABLE_END); i++) {
0189         if ((i < 2) && (has_N44_O17_errata[policy->cpu]))
0190             p4clockmod_table[i].frequency = CPUFREQ_ENTRY_INVALID;
0191         else
0192             p4clockmod_table[i].frequency = (stock_freq * i)/8;
0193     }
0194
0195     /* cpuinfo and default policy values */
0196
0197     /* the transition latency is set to be 1 higher than the maximum
0198      * transition latency of the ondemand governor */
0199     policy->cpuinfo.transition_latency = 10000001;
0200     policy->freq_table = &p4clockmod_table[0];
0201
0202     return 0;
0203 }
0204
0205
0206 static unsigned int cpufreq_p4_get(unsigned int cpu)
0207 {
0208     u32 l, h;
0209
0210     rdmsr_on_cpu(cpu, MSR_IA32_THERM_CONTROL, &l, &h);
0211
0212     if (l & 0x10) {
0213         l = l >> 1;
0214         l &= 0x7;
0215     } else
0216         l = DC_DISABLE;
0217
0218     if (l != DC_DISABLE)
0219         return stock_freq * l / 8;
0220
0221     return stock_freq;
0222 }
0223
0224 static struct cpufreq_driver p4clockmod_driver = {
0225     .verify     = cpufreq_generic_frequency_table_verify,
0226     .target_index   = cpufreq_p4_target,
0227     .init       = cpufreq_p4_cpu_init,
0228     .get        = cpufreq_p4_get,
0229     .name       = "p4-clockmod",
0230     .attr       = cpufreq_generic_attr,
0231 };
0232
0233 static const struct x86_cpu_id cpufreq_p4_id[] = {
0234     X86_MATCH_VENDOR_FEATURE(INTEL, X86_FEATURE_ACC, NULL),
0235     {}
0236 };
0237
0238 /*
0239  * Intentionally no MODULE_DEVICE_TABLE here: this driver should not
0240  * be auto loaded.  Please don't add one.
0241  */
0242
0243 static int __init cpufreq_p4_init(void)
0244 {
0245     int ret;
0246
0247     /*
0248      * THERM_CONTROL is architectural for IA32 now, so
0249      * we can rely on the capability checks
0250      */
0251     if (!x86_match_cpu(cpufreq_p4_id) || !boot_cpu_has(X86_FEATURE_ACPI))
0252         return -ENODEV;
0253
0254     ret = cpufreq_register_driver(&p4clockmod_driver);
0255     if (!ret)
0256         pr_info("P4/Xeon(TM) CPU On-Demand Clock Modulation available\n");
0257
0258     return ret;
0259 }
0260
0261
0262 static void __exit cpufreq_p4_exit(void)
0263 {
0264     cpufreq_unregister_driver(&p4clockmod_driver);
0265 }
0266
0267
0268 MODULE_AUTHOR("Zwane Mwaikambo <zwane@commfireservices.com>");
0269 MODULE_DESCRIPTION("cpufreq driver for Pentium(TM) 4/Xeon(TM)");
0270 MODULE_LICENSE("GPL");
0271
0272 late_initcall(cpufreq_p4_init);
0273 module_exit(cpufreq_p4_exit);