drivers/cpufreq/mediatek-cpufreq-hw.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2020 MediaTek Inc.
0004  */
0005
0006 #include <linux/bitfield.h>
0007 #include <linux/cpufreq.h>
0008 #include <linux/energy_model.h>
0009 #include <linux/init.h>
0010 #include <linux/iopoll.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_platform.h>
0015 #include <linux/slab.h>
0016
0017 #define LUT_MAX_ENTRIES         32U
0018 #define LUT_FREQ            GENMASK(11, 0)
0019 #define LUT_ROW_SIZE            0x4
0020 #define CPUFREQ_HW_STATUS       BIT(0)
0021 #define SVS_HW_STATUS           BIT(1)
0022 #define POLL_USEC           1000
0023 #define TIMEOUT_USEC            300000
0024
0025 enum {
0026     REG_FREQ_LUT_TABLE,
0027     REG_FREQ_ENABLE,
0028     REG_FREQ_PERF_STATE,
0029     REG_FREQ_HW_STATE,
0030     REG_EM_POWER_TBL,
0031     REG_FREQ_LATENCY,
0032
0033     REG_ARRAY_SIZE,
0034 };
0035
0036 struct mtk_cpufreq_data {
0037     struct cpufreq_frequency_table *table;
0038     void __iomem *reg_bases[REG_ARRAY_SIZE];
0039     struct resource *res;
0040     void __iomem *base;
0041     int nr_opp;
0042 };
0043
0044 static const u16 cpufreq_mtk_offsets[REG_ARRAY_SIZE] = {
0045     [REG_FREQ_LUT_TABLE]    = 0x0,
0046     [REG_FREQ_ENABLE]   = 0x84,
0047     [REG_FREQ_PERF_STATE]   = 0x88,
0048     [REG_FREQ_HW_STATE] = 0x8c,
0049     [REG_EM_POWER_TBL]  = 0x90,
0050     [REG_FREQ_LATENCY]  = 0x110,
0051 };
0052
0053 static int __maybe_unused
0054 mtk_cpufreq_get_cpu_power(struct device *cpu_dev, unsigned long *uW,
0055               unsigned long *KHz)
0056 {
0057     struct mtk_cpufreq_data *data;
0058     struct cpufreq_policy *policy;
0059     int i;
0060
0061     policy = cpufreq_cpu_get_raw(cpu_dev->id);
0062     if (!policy)
0063         return 0;
0064
0065     data = policy->driver_data;
0066
0067     for (i = 0; i < data->nr_opp; i++) {
0068         if (data->table[i].frequency < *KHz)
0069             break;
0070     }
0071     i--;
0072
0073     *KHz = data->table[i].frequency;
0074     /* Provide micro-Watts value to the Energy Model */
0075     *uW = readl_relaxed(data->reg_bases[REG_EM_POWER_TBL] +
0076                 i * LUT_ROW_SIZE);
0077
0078     return 0;
0079 }
0080
0081 static int mtk_cpufreq_hw_target_index(struct cpufreq_policy *policy,
0082                        unsigned int index)
0083 {
0084     struct mtk_cpufreq_data *data = policy->driver_data;
0085
0086     writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]);
0087
0088     return 0;
0089 }
0090
0091 static unsigned int mtk_cpufreq_hw_get(unsigned int cpu)
0092 {
0093     struct mtk_cpufreq_data *data;
0094     struct cpufreq_policy *policy;
0095     unsigned int index;
0096
0097     policy = cpufreq_cpu_get_raw(cpu);
0098     if (!policy)
0099         return 0;
0100
0101     data = policy->driver_data;
0102
0103     index = readl_relaxed(data->reg_bases[REG_FREQ_PERF_STATE]);
0104     index = min(index, LUT_MAX_ENTRIES - 1);
0105
0106     return data->table[index].frequency;
0107 }
0108
0109 static unsigned int mtk_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
0110                            unsigned int target_freq)
0111 {
0112     struct mtk_cpufreq_data *data = policy->driver_data;
0113     unsigned int index;
0114
0115     index = cpufreq_table_find_index_dl(policy, target_freq, false);
0116
0117     writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]);
0118
0119     return policy->freq_table[index].frequency;
0120 }
0121
0122 static int mtk_cpu_create_freq_table(struct platform_device *pdev,
0123                      struct mtk_cpufreq_data *data)
0124 {
0125     struct device *dev = &pdev->dev;
0126     u32 temp, i, freq, prev_freq = 0;
0127     void __iomem *base_table;
0128
0129     data->table = devm_kcalloc(dev, LUT_MAX_ENTRIES + 1,
0130                    sizeof(*data->table), GFP_KERNEL);
0131     if (!data->table)
0132         return -ENOMEM;
0133
0134     base_table = data->reg_bases[REG_FREQ_LUT_TABLE];
0135
0136     for (i = 0; i < LUT_MAX_ENTRIES; i++) {
0137         temp = readl_relaxed(base_table + (i * LUT_ROW_SIZE));
0138         freq = FIELD_GET(LUT_FREQ, temp) * 1000;
0139
0140         if (freq == prev_freq)
0141             break;
0142
0143         data->table[i].frequency = freq;
0144
0145         dev_dbg(dev, "index=%d freq=%d\n", i, data->table[i].frequency);
0146
0147         prev_freq = freq;
0148     }
0149
0150     data->table[i].frequency = CPUFREQ_TABLE_END;
0151     data->nr_opp = i;
0152
0153     return 0;
0154 }
0155
0156 static int mtk_cpu_resources_init(struct platform_device *pdev,
0157                   struct cpufreq_policy *policy,
0158                   const u16 *offsets)
0159 {
0160     struct mtk_cpufreq_data *data;
0161     struct device *dev = &pdev->dev;
0162     struct resource *res;
0163     void __iomem *base;
0164     int ret, i;
0165     int index;
0166
0167     data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
0168     if (!data)
0169         return -ENOMEM;
0170
0171     index = of_perf_domain_get_sharing_cpumask(policy->cpu, "performance-domains",
0172                            "#performance-domain-cells",
0173                            policy->cpus);
0174     if (index < 0)
0175         return index;
0176
0177     res = platform_get_resource(pdev, IORESOURCE_MEM, index);
0178     if (!res) {
0179         dev_err(dev, "failed to get mem resource %d\n", index);
0180         return -ENODEV;
0181     }
0182
0183     if (!request_mem_region(res->start, resource_size(res), res->name)) {
0184         dev_err(dev, "failed to request resource %pR\n", res);
0185         return -EBUSY;
0186     }
0187
0188     base = ioremap(res->start, resource_size(res));
0189     if (!base) {
0190         dev_err(dev, "failed to map resource %pR\n", res);
0191         ret = -ENOMEM;
0192         goto release_region;
0193     }
0194
0195     data->base = base;
0196     data->res = res;
0197
0198     for (i = REG_FREQ_LUT_TABLE; i < REG_ARRAY_SIZE; i++)
0199         data->reg_bases[i] = base + offsets[i];
0200
0201     ret = mtk_cpu_create_freq_table(pdev, data);
0202     if (ret) {
0203         dev_info(dev, "Domain-%d failed to create freq table\n", index);
0204         return ret;
0205     }
0206
0207     policy->freq_table = data->table;
0208     policy->driver_data = data;
0209
0210     return 0;
0211 release_region:
0212     release_mem_region(res->start, resource_size(res));
0213     return ret;
0214 }
0215
0216 static int mtk_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
0217 {
0218     struct platform_device *pdev = cpufreq_get_driver_data();
0219     int sig, pwr_hw = CPUFREQ_HW_STATUS | SVS_HW_STATUS;
0220     struct mtk_cpufreq_data *data;
0221     unsigned int latency;
0222     int ret;
0223
0224     /* Get the bases of cpufreq for domains */
0225     ret = mtk_cpu_resources_init(pdev, policy, platform_get_drvdata(pdev));
0226     if (ret) {
0227         dev_info(&pdev->dev, "CPUFreq resource init failed\n");
0228         return ret;
0229     }
0230
0231     data = policy->driver_data;
0232
0233     latency = readl_relaxed(data->reg_bases[REG_FREQ_LATENCY]) * 1000;
0234     if (!latency)
0235         latency = CPUFREQ_ETERNAL;
0236
0237     policy->cpuinfo.transition_latency = latency;
0238     policy->fast_switch_possible = true;
0239
0240     /* HW should be in enabled state to proceed now */
0241     writel_relaxed(0x1, data->reg_bases[REG_FREQ_ENABLE]);
0242     if (readl_poll_timeout(data->reg_bases[REG_FREQ_HW_STATE], sig,
0243                    (sig & pwr_hw) == pwr_hw, POLL_USEC,
0244                    TIMEOUT_USEC)) {
0245         if (!(sig & CPUFREQ_HW_STATUS)) {
0246             pr_info("cpufreq hardware of CPU%d is not enabled\n",
0247                 policy->cpu);
0248             return -ENODEV;
0249         }
0250
0251         pr_info("SVS of CPU%d is not enabled\n", policy->cpu);
0252     }
0253
0254     return 0;
0255 }
0256
0257 static int mtk_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
0258 {
0259     struct mtk_cpufreq_data *data = policy->driver_data;
0260     struct resource *res = data->res;
0261     void __iomem *base = data->base;
0262
0263     /* HW should be in paused state now */
0264     writel_relaxed(0x0, data->reg_bases[REG_FREQ_ENABLE]);
0265     iounmap(base);
0266     release_mem_region(res->start, resource_size(res));
0267
0268     return 0;
0269 }
0270
0271 static void mtk_cpufreq_register_em(struct cpufreq_policy *policy)
0272 {
0273     struct em_data_callback em_cb = EM_DATA_CB(mtk_cpufreq_get_cpu_power);
0274     struct mtk_cpufreq_data *data = policy->driver_data;
0275
0276     em_dev_register_perf_domain(get_cpu_device(policy->cpu), data->nr_opp,
0277                     &em_cb, policy->cpus, true);
0278 }
0279
0280 static struct cpufreq_driver cpufreq_mtk_hw_driver = {
0281     .flags      = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
0282               CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
0283               CPUFREQ_IS_COOLING_DEV,
0284     .verify     = cpufreq_generic_frequency_table_verify,
0285     .target_index   = mtk_cpufreq_hw_target_index,
0286     .get        = mtk_cpufreq_hw_get,
0287     .init       = mtk_cpufreq_hw_cpu_init,
0288     .exit       = mtk_cpufreq_hw_cpu_exit,
0289     .register_em    = mtk_cpufreq_register_em,
0290     .fast_switch    = mtk_cpufreq_hw_fast_switch,
0291     .name       = "mtk-cpufreq-hw",
0292     .attr       = cpufreq_generic_attr,
0293 };
0294
0295 static int mtk_cpufreq_hw_driver_probe(struct platform_device *pdev)
0296 {
0297     const void *data;
0298     int ret;
0299
0300     data = of_device_get_match_data(&pdev->dev);
0301     if (!data)
0302         return -EINVAL;
0303
0304     platform_set_drvdata(pdev, (void *) data);
0305     cpufreq_mtk_hw_driver.driver_data = pdev;
0306
0307     ret = cpufreq_register_driver(&cpufreq_mtk_hw_driver);
0308     if (ret)
0309         dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
0310
0311     return ret;
0312 }
0313
0314 static int mtk_cpufreq_hw_driver_remove(struct platform_device *pdev)
0315 {
0316     return cpufreq_unregister_driver(&cpufreq_mtk_hw_driver);
0317 }
0318
0319 static const struct of_device_id mtk_cpufreq_hw_match[] = {
0320     { .compatible = "mediatek,cpufreq-hw", .data = &cpufreq_mtk_offsets },
0321     {}
0322 };
0323
0324 static struct platform_driver mtk_cpufreq_hw_driver = {
0325     .probe = mtk_cpufreq_hw_driver_probe,
0326     .remove = mtk_cpufreq_hw_driver_remove,
0327     .driver = {
0328         .name = "mtk-cpufreq-hw",
0329         .of_match_table = mtk_cpufreq_hw_match,
0330     },
0331 };
0332 module_platform_driver(mtk_cpufreq_hw_driver);
0333
0334 MODULE_AUTHOR("Hector Yuan <hector.yuan@mediatek.com>");
0335 MODULE_DESCRIPTION("Mediatek cpufreq-hw driver");
0336 MODULE_LICENSE("GPL v2");