drivers/cpufreq/maple-cpufreq.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Copyright (C) 2011 Dmitry Eremin-Solenikov
0004  *  Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
0005  *  and                       Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
0006  *
0007  * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
0008  * that is iMac G5 and latest single CPU desktop.
0009  */
0010
0011 #undef DEBUG
0012
0013 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0014
0015 #include <linux/module.h>
0016 #include <linux/types.h>
0017 #include <linux/errno.h>
0018 #include <linux/kernel.h>
0019 #include <linux/delay.h>
0020 #include <linux/sched.h>
0021 #include <linux/cpufreq.h>
0022 #include <linux/init.h>
0023 #include <linux/completion.h>
0024 #include <linux/mutex.h>
0025 #include <linux/time.h>
0026 #include <linux/of_device.h>
0027
0028 #define DBG(fmt...) pr_debug(fmt)
0029
0030 /* see 970FX user manual */
0031
0032 #define SCOM_PCR 0x0aa001           /* PCR scom addr */
0033
0034 #define PCR_HILO_SELECT     0x80000000U /* 1 = PCR, 0 = PCRH */
0035 #define PCR_SPEED_FULL      0x00000000U /* 1:1 speed value */
0036 #define PCR_SPEED_HALF      0x00020000U /* 1:2 speed value */
0037 #define PCR_SPEED_QUARTER   0x00040000U /* 1:4 speed value */
0038 #define PCR_SPEED_MASK      0x000e0000U /* speed mask */
0039 #define PCR_SPEED_SHIFT     17
0040 #define PCR_FREQ_REQ_VALID  0x00010000U /* freq request valid */
0041 #define PCR_VOLT_REQ_VALID  0x00008000U /* volt request valid */
0042 #define PCR_TARGET_TIME_MASK    0x00006000U /* target time */
0043 #define PCR_STATLAT_MASK    0x00001f00U /* STATLAT value */
0044 #define PCR_SNOOPLAT_MASK   0x000000f0U /* SNOOPLAT value */
0045 #define PCR_SNOOPACC_MASK   0x0000000fU /* SNOOPACC value */
0046
0047 #define SCOM_PSR 0x408001           /* PSR scom addr */
0048 /* warning: PSR is a 64 bits register */
0049 #define PSR_CMD_RECEIVED    0x2000000000000000U   /* command received */
0050 #define PSR_CMD_COMPLETED   0x1000000000000000U   /* command completed */
0051 #define PSR_CUR_SPEED_MASK  0x0300000000000000U   /* current speed */
0052 #define PSR_CUR_SPEED_SHIFT (56)
0053
0054 /*
0055  * The G5 only supports two frequencies (Quarter speed is not supported)
0056  */
0057 #define CPUFREQ_HIGH                  0
0058 #define CPUFREQ_LOW                   1
0059
0060 static struct cpufreq_frequency_table maple_cpu_freqs[] = {
0061     {0, CPUFREQ_HIGH,       0},
0062     {0, CPUFREQ_LOW,        0},
0063     {0, 0,              CPUFREQ_TABLE_END},
0064 };
0065
0066 /* Power mode data is an array of the 32 bits PCR values to use for
0067  * the various frequencies, retrieved from the device-tree
0068  */
0069 static int maple_pmode_cur;
0070
0071 static const u32 *maple_pmode_data;
0072 static int maple_pmode_max;
0073
0074 /*
0075  * SCOM based frequency switching for 970FX rev3
0076  */
0077 static int maple_scom_switch_freq(int speed_mode)
0078 {
0079     unsigned long flags;
0080     int to;
0081
0082     local_irq_save(flags);
0083
0084     /* Clear PCR high */
0085     scom970_write(SCOM_PCR, 0);
0086     /* Clear PCR low */
0087     scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
0088     /* Set PCR low */
0089     scom970_write(SCOM_PCR, PCR_HILO_SELECT |
0090               maple_pmode_data[speed_mode]);
0091
0092     /* Wait for completion */
0093     for (to = 0; to < 10; to++) {
0094         unsigned long psr = scom970_read(SCOM_PSR);
0095
0096         if ((psr & PSR_CMD_RECEIVED) == 0 &&
0097             (((psr >> PSR_CUR_SPEED_SHIFT) ^
0098               (maple_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
0099             == 0)
0100             break;
0101         if (psr & PSR_CMD_COMPLETED)
0102             break;
0103         udelay(100);
0104     }
0105
0106     local_irq_restore(flags);
0107
0108     maple_pmode_cur = speed_mode;
0109     ppc_proc_freq = maple_cpu_freqs[speed_mode].frequency * 1000ul;
0110
0111     return 0;
0112 }
0113
0114 static int maple_scom_query_freq(void)
0115 {
0116     unsigned long psr = scom970_read(SCOM_PSR);
0117     int i;
0118
0119     for (i = 0; i <= maple_pmode_max; i++)
0120         if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
0121               (maple_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
0122             break;
0123     return i;
0124 }
0125
0126 /*
0127  * Common interface to the cpufreq core
0128  */
0129
0130 static int maple_cpufreq_target(struct cpufreq_policy *policy,
0131     unsigned int index)
0132 {
0133     return maple_scom_switch_freq(index);
0134 }
0135
0136 static unsigned int maple_cpufreq_get_speed(unsigned int cpu)
0137 {
0138     return maple_cpu_freqs[maple_pmode_cur].frequency;
0139 }
0140
0141 static int maple_cpufreq_cpu_init(struct cpufreq_policy *policy)
0142 {
0143     cpufreq_generic_init(policy, maple_cpu_freqs, 12000);
0144     return 0;
0145 }
0146
0147 static struct cpufreq_driver maple_cpufreq_driver = {
0148     .name       = "maple",
0149     .flags      = CPUFREQ_CONST_LOOPS,
0150     .init       = maple_cpufreq_cpu_init,
0151     .verify     = cpufreq_generic_frequency_table_verify,
0152     .target_index   = maple_cpufreq_target,
0153     .get        = maple_cpufreq_get_speed,
0154     .attr       = cpufreq_generic_attr,
0155 };
0156
0157 static int __init maple_cpufreq_init(void)
0158 {
0159     struct device_node *cpunode;
0160     unsigned int psize;
0161     unsigned long max_freq;
0162     const u32 *valp;
0163     u32 pvr_hi;
0164     int rc = -ENODEV;
0165
0166     /*
0167      * Behave here like powermac driver which checks machine compatibility
0168      * to ease merging of two drivers in future.
0169      */
0170     if (!of_machine_is_compatible("Momentum,Maple") &&
0171         !of_machine_is_compatible("Momentum,Apache"))
0172         return 0;
0173
0174     /* Get first CPU node */
0175     cpunode = of_cpu_device_node_get(0);
0176     if (cpunode == NULL) {
0177         pr_err("Can't find any CPU 0 node\n");
0178         goto bail_noprops;
0179     }
0180
0181     /* Check 970FX for now */
0182     /* we actually don't care on which CPU to access PVR */
0183     pvr_hi = PVR_VER(mfspr(SPRN_PVR));
0184     if (pvr_hi != 0x3c && pvr_hi != 0x44) {
0185         pr_err("Unsupported CPU version (%x)\n", pvr_hi);
0186         goto bail_noprops;
0187     }
0188
0189     /* Look for the powertune data in the device-tree */
0190     /*
0191      * On Maple this property is provided by PIBS in dual-processor config,
0192      * not provided by PIBS in CPU0 config and also not provided by SLOF,
0193      * so YMMV
0194      */
0195     maple_pmode_data = of_get_property(cpunode, "power-mode-data", &psize);
0196     if (!maple_pmode_data) {
0197         DBG("No power-mode-data !\n");
0198         goto bail_noprops;
0199     }
0200     maple_pmode_max = psize / sizeof(u32) - 1;
0201
0202     /*
0203      * From what I see, clock-frequency is always the maximal frequency.
0204      * The current driver can not slew sysclk yet, so we really only deal
0205      * with powertune steps for now. We also only implement full freq and
0206      * half freq in this version. So far, I haven't yet seen a machine
0207      * supporting anything else.
0208      */
0209     valp = of_get_property(cpunode, "clock-frequency", NULL);
0210     if (!valp)
0211         goto bail_noprops;
0212     max_freq = (*valp)/1000;
0213     maple_cpu_freqs[0].frequency = max_freq;
0214     maple_cpu_freqs[1].frequency = max_freq/2;
0215
0216     /* Force apply current frequency to make sure everything is in
0217      * sync (voltage is right for example). Firmware may leave us with
0218      * a strange setting ...
0219      */
0220     msleep(10);
0221     maple_pmode_cur = -1;
0222     maple_scom_switch_freq(maple_scom_query_freq());
0223
0224     pr_info("Registering Maple CPU frequency driver\n");
0225     pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
0226         maple_cpu_freqs[1].frequency/1000,
0227         maple_cpu_freqs[0].frequency/1000,
0228         maple_cpu_freqs[maple_pmode_cur].frequency/1000);
0229
0230     rc = cpufreq_register_driver(&maple_cpufreq_driver);
0231
0232 bail_noprops:
0233     of_node_put(cpunode);
0234
0235     return rc;
0236 }
0237
0238 module_init(maple_cpufreq_init);
0239
0240
0241 MODULE_LICENSE("GPL");