drivers/counter/stm32-timer-cnt.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * STM32 Timer Encoder and Counter driver
0004  *
0005  * Copyright (C) STMicroelectronics 2018
0006  *
0007  * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
0008  *
0009  */
0010 #include <linux/counter.h>
0011 #include <linux/mfd/stm32-timers.h>
0012 #include <linux/mod_devicetable.h>
0013 #include <linux/module.h>
0014 #include <linux/pinctrl/consumer.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/types.h>
0017
0018 #define TIM_CCMR_CCXS   (BIT(8) | BIT(0))
0019 #define TIM_CCMR_MASK   (TIM_CCMR_CC1S | TIM_CCMR_CC2S | \
0020              TIM_CCMR_IC1F | TIM_CCMR_IC2F)
0021 #define TIM_CCER_MASK   (TIM_CCER_CC1P | TIM_CCER_CC1NP | \
0022              TIM_CCER_CC2P | TIM_CCER_CC2NP)
0023
0024 struct stm32_timer_regs {
0025     u32 cr1;
0026     u32 cnt;
0027     u32 smcr;
0028     u32 arr;
0029 };
0030
0031 struct stm32_timer_cnt {
0032     struct regmap *regmap;
0033     struct clk *clk;
0034     u32 max_arr;
0035     bool enabled;
0036     struct stm32_timer_regs bak;
0037 };
0038
0039 static const enum counter_function stm32_count_functions[] = {
0040     COUNTER_FUNCTION_INCREASE,
0041     COUNTER_FUNCTION_QUADRATURE_X2_A,
0042     COUNTER_FUNCTION_QUADRATURE_X2_B,
0043     COUNTER_FUNCTION_QUADRATURE_X4,
0044 };
0045
0046 static int stm32_count_read(struct counter_device *counter,
0047                 struct counter_count *count, u64 *val)
0048 {
0049     struct stm32_timer_cnt *const priv = counter_priv(counter);
0050     u32 cnt;
0051
0052     regmap_read(priv->regmap, TIM_CNT, &cnt);
0053     *val = cnt;
0054
0055     return 0;
0056 }
0057
0058 static int stm32_count_write(struct counter_device *counter,
0059                  struct counter_count *count, const u64 val)
0060 {
0061     struct stm32_timer_cnt *const priv = counter_priv(counter);
0062     u32 ceiling;
0063
0064     regmap_read(priv->regmap, TIM_ARR, &ceiling);
0065     if (val > ceiling)
0066         return -EINVAL;
0067
0068     return regmap_write(priv->regmap, TIM_CNT, val);
0069 }
0070
0071 static int stm32_count_function_read(struct counter_device *counter,
0072                      struct counter_count *count,
0073                      enum counter_function *function)
0074 {
0075     struct stm32_timer_cnt *const priv = counter_priv(counter);
0076     u32 smcr;
0077
0078     regmap_read(priv->regmap, TIM_SMCR, &smcr);
0079
0080     switch (smcr & TIM_SMCR_SMS) {
0081     case TIM_SMCR_SMS_SLAVE_MODE_DISABLED:
0082         *function = COUNTER_FUNCTION_INCREASE;
0083         return 0;
0084     case TIM_SMCR_SMS_ENCODER_MODE_1:
0085         *function = COUNTER_FUNCTION_QUADRATURE_X2_A;
0086         return 0;
0087     case TIM_SMCR_SMS_ENCODER_MODE_2:
0088         *function = COUNTER_FUNCTION_QUADRATURE_X2_B;
0089         return 0;
0090     case TIM_SMCR_SMS_ENCODER_MODE_3:
0091         *function = COUNTER_FUNCTION_QUADRATURE_X4;
0092         return 0;
0093     default:
0094         return -EINVAL;
0095     }
0096 }
0097
0098 static int stm32_count_function_write(struct counter_device *counter,
0099                       struct counter_count *count,
0100                       enum counter_function function)
0101 {
0102     struct stm32_timer_cnt *const priv = counter_priv(counter);
0103     u32 cr1, sms;
0104
0105     switch (function) {
0106     case COUNTER_FUNCTION_INCREASE:
0107         sms = TIM_SMCR_SMS_SLAVE_MODE_DISABLED;
0108         break;
0109     case COUNTER_FUNCTION_QUADRATURE_X2_A:
0110         sms = TIM_SMCR_SMS_ENCODER_MODE_1;
0111         break;
0112     case COUNTER_FUNCTION_QUADRATURE_X2_B:
0113         sms = TIM_SMCR_SMS_ENCODER_MODE_2;
0114         break;
0115     case COUNTER_FUNCTION_QUADRATURE_X4:
0116         sms = TIM_SMCR_SMS_ENCODER_MODE_3;
0117         break;
0118     default:
0119         return -EINVAL;
0120     }
0121
0122     /* Store enable status */
0123     regmap_read(priv->regmap, TIM_CR1, &cr1);
0124
0125     regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
0126
0127     regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
0128
0129     /* Make sure that registers are updated */
0130     regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
0131
0132     /* Restore the enable status */
0133     regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);
0134
0135     return 0;
0136 }
0137
0138 static int stm32_count_direction_read(struct counter_device *counter,
0139                       struct counter_count *count,
0140                       enum counter_count_direction *direction)
0141 {
0142     struct stm32_timer_cnt *const priv = counter_priv(counter);
0143     u32 cr1;
0144
0145     regmap_read(priv->regmap, TIM_CR1, &cr1);
0146     *direction = (cr1 & TIM_CR1_DIR) ? COUNTER_COUNT_DIRECTION_BACKWARD :
0147         COUNTER_COUNT_DIRECTION_FORWARD;
0148
0149     return 0;
0150 }
0151
0152 static int stm32_count_ceiling_read(struct counter_device *counter,
0153                     struct counter_count *count, u64 *ceiling)
0154 {
0155     struct stm32_timer_cnt *const priv = counter_priv(counter);
0156     u32 arr;
0157
0158     regmap_read(priv->regmap, TIM_ARR, &arr);
0159
0160     *ceiling = arr;
0161
0162     return 0;
0163 }
0164
0165 static int stm32_count_ceiling_write(struct counter_device *counter,
0166                      struct counter_count *count, u64 ceiling)
0167 {
0168     struct stm32_timer_cnt *const priv = counter_priv(counter);
0169
0170     if (ceiling > priv->max_arr)
0171         return -ERANGE;
0172
0173     /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
0174     regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
0175     regmap_write(priv->regmap, TIM_ARR, ceiling);
0176
0177     return 0;
0178 }
0179
0180 static int stm32_count_enable_read(struct counter_device *counter,
0181                    struct counter_count *count, u8 *enable)
0182 {
0183     struct stm32_timer_cnt *const priv = counter_priv(counter);
0184     u32 cr1;
0185
0186     regmap_read(priv->regmap, TIM_CR1, &cr1);
0187
0188     *enable = cr1 & TIM_CR1_CEN;
0189
0190     return 0;
0191 }
0192
0193 static int stm32_count_enable_write(struct counter_device *counter,
0194                     struct counter_count *count, u8 enable)
0195 {
0196     struct stm32_timer_cnt *const priv = counter_priv(counter);
0197     u32 cr1;
0198
0199     if (enable) {
0200         regmap_read(priv->regmap, TIM_CR1, &cr1);
0201         if (!(cr1 & TIM_CR1_CEN))
0202             clk_enable(priv->clk);
0203
0204         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
0205                    TIM_CR1_CEN);
0206     } else {
0207         regmap_read(priv->regmap, TIM_CR1, &cr1);
0208         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
0209         if (cr1 & TIM_CR1_CEN)
0210             clk_disable(priv->clk);
0211     }
0212
0213     /* Keep enabled state to properly handle low power states */
0214     priv->enabled = enable;
0215
0216     return 0;
0217 }
0218
0219 static struct counter_comp stm32_count_ext[] = {
0220     COUNTER_COMP_DIRECTION(stm32_count_direction_read),
0221     COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write),
0222     COUNTER_COMP_CEILING(stm32_count_ceiling_read,
0223                  stm32_count_ceiling_write),
0224 };
0225
0226 static const enum counter_synapse_action stm32_synapse_actions[] = {
0227     COUNTER_SYNAPSE_ACTION_NONE,
0228     COUNTER_SYNAPSE_ACTION_BOTH_EDGES
0229 };
0230
0231 static int stm32_action_read(struct counter_device *counter,
0232                  struct counter_count *count,
0233                  struct counter_synapse *synapse,
0234                  enum counter_synapse_action *action)
0235 {
0236     enum counter_function function;
0237     int err;
0238
0239     err = stm32_count_function_read(counter, count, &function);
0240     if (err)
0241         return err;
0242
0243     switch (function) {
0244     case COUNTER_FUNCTION_INCREASE:
0245         /* counts on internal clock when CEN=1 */
0246         *action = COUNTER_SYNAPSE_ACTION_NONE;
0247         return 0;
0248     case COUNTER_FUNCTION_QUADRATURE_X2_A:
0249         /* counts up/down on TI1FP1 edge depending on TI2FP2 level */
0250         if (synapse->signal->id == count->synapses[0].signal->id)
0251             *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
0252         else
0253             *action = COUNTER_SYNAPSE_ACTION_NONE;
0254         return 0;
0255     case COUNTER_FUNCTION_QUADRATURE_X2_B:
0256         /* counts up/down on TI2FP2 edge depending on TI1FP1 level */
0257         if (synapse->signal->id == count->synapses[1].signal->id)
0258             *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
0259         else
0260             *action = COUNTER_SYNAPSE_ACTION_NONE;
0261         return 0;
0262     case COUNTER_FUNCTION_QUADRATURE_X4:
0263         /* counts up/down on both TI1FP1 and TI2FP2 edges */
0264         *action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
0265         return 0;
0266     default:
0267         return -EINVAL;
0268     }
0269 }
0270
0271 static const struct counter_ops stm32_timer_cnt_ops = {
0272     .count_read = stm32_count_read,
0273     .count_write = stm32_count_write,
0274     .function_read = stm32_count_function_read,
0275     .function_write = stm32_count_function_write,
0276     .action_read = stm32_action_read,
0277 };
0278
0279 static struct counter_signal stm32_signals[] = {
0280     {
0281         .id = 0,
0282         .name = "Channel 1 Quadrature A"
0283     },
0284     {
0285         .id = 1,
0286         .name = "Channel 1 Quadrature B"
0287     }
0288 };
0289
0290 static struct counter_synapse stm32_count_synapses[] = {
0291     {
0292         .actions_list = stm32_synapse_actions,
0293         .num_actions = ARRAY_SIZE(stm32_synapse_actions),
0294         .signal = &stm32_signals[0]
0295     },
0296     {
0297         .actions_list = stm32_synapse_actions,
0298         .num_actions = ARRAY_SIZE(stm32_synapse_actions),
0299         .signal = &stm32_signals[1]
0300     }
0301 };
0302
0303 static struct counter_count stm32_counts = {
0304     .id = 0,
0305     .name = "Channel 1 Count",
0306     .functions_list = stm32_count_functions,
0307     .num_functions = ARRAY_SIZE(stm32_count_functions),
0308     .synapses = stm32_count_synapses,
0309     .num_synapses = ARRAY_SIZE(stm32_count_synapses),
0310     .ext = stm32_count_ext,
0311     .num_ext = ARRAY_SIZE(stm32_count_ext)
0312 };
0313
0314 static int stm32_timer_cnt_probe(struct platform_device *pdev)
0315 {
0316     struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
0317     struct device *dev = &pdev->dev;
0318     struct stm32_timer_cnt *priv;
0319     struct counter_device *counter;
0320     int ret;
0321
0322     if (IS_ERR_OR_NULL(ddata))
0323         return -EINVAL;
0324
0325     counter = devm_counter_alloc(dev, sizeof(*priv));
0326     if (!counter)
0327         return -ENOMEM;
0328
0329     priv = counter_priv(counter);
0330
0331     priv->regmap = ddata->regmap;
0332     priv->clk = ddata->clk;
0333     priv->max_arr = ddata->max_arr;
0334
0335     counter->name = dev_name(dev);
0336     counter->parent = dev;
0337     counter->ops = &stm32_timer_cnt_ops;
0338     counter->counts = &stm32_counts;
0339     counter->num_counts = 1;
0340     counter->signals = stm32_signals;
0341     counter->num_signals = ARRAY_SIZE(stm32_signals);
0342
0343     platform_set_drvdata(pdev, priv);
0344
0345     /* Register Counter device */
0346     ret = devm_counter_add(dev, counter);
0347     if (ret < 0)
0348         dev_err_probe(dev, ret, "Failed to add counter\n");
0349
0350     return ret;
0351 }
0352
0353 static int __maybe_unused stm32_timer_cnt_suspend(struct device *dev)
0354 {
0355     struct stm32_timer_cnt *priv = dev_get_drvdata(dev);
0356
0357     /* Only take care of enabled counter: don't disturb other MFD child */
0358     if (priv->enabled) {
0359         /* Backup registers that may get lost in low power mode */
0360         regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);
0361         regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);
0362         regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);
0363         regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);
0364
0365         /* Disable the counter */
0366         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
0367         clk_disable(priv->clk);
0368     }
0369
0370     return pinctrl_pm_select_sleep_state(dev);
0371 }
0372
0373 static int __maybe_unused stm32_timer_cnt_resume(struct device *dev)
0374 {
0375     struct stm32_timer_cnt *priv = dev_get_drvdata(dev);
0376     int ret;
0377
0378     ret = pinctrl_pm_select_default_state(dev);
0379     if (ret)
0380         return ret;
0381
0382     if (priv->enabled) {
0383         clk_enable(priv->clk);
0384
0385         /* Restore registers that may have been lost */
0386         regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);
0387         regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);
0388         regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);
0389
0390         /* Also re-enables the counter */
0391         regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);
0392     }
0393
0394     return 0;
0395 }
0396
0397 static SIMPLE_DEV_PM_OPS(stm32_timer_cnt_pm_ops, stm32_timer_cnt_suspend,
0398              stm32_timer_cnt_resume);
0399
0400 static const struct of_device_id stm32_timer_cnt_of_match[] = {
0401     { .compatible = "st,stm32-timer-counter", },
0402     {},
0403 };
0404 MODULE_DEVICE_TABLE(of, stm32_timer_cnt_of_match);
0405
0406 static struct platform_driver stm32_timer_cnt_driver = {
0407     .probe = stm32_timer_cnt_probe,
0408     .driver = {
0409         .name = "stm32-timer-counter",
0410         .of_match_table = stm32_timer_cnt_of_match,
0411         .pm = &stm32_timer_cnt_pm_ops,
0412     },
0413 };
0414 module_platform_driver(stm32_timer_cnt_driver);
0415
0416 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
0417 MODULE_ALIAS("platform:stm32-timer-counter");
0418 MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver");
0419 MODULE_LICENSE("GPL v2");