drivers/clocksource/timer-vf-pit.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2012-2013 Freescale Semiconductor, Inc.
0004  */
0005
0006 #include <linux/interrupt.h>
0007 #include <linux/clockchips.h>
0008 #include <linux/clk.h>
0009 #include <linux/of_address.h>
0010 #include <linux/of_irq.h>
0011 #include <linux/sched_clock.h>
0012
0013 /*
0014  * Each pit takes 0x10 Bytes register space
0015  */
0016 #define PITMCR      0x00
0017 #define PIT0_OFFSET 0x100
0018 #define PITn_OFFSET(n)  (PIT0_OFFSET + 0x10 * (n))
0019 #define PITLDVAL    0x00
0020 #define PITCVAL     0x04
0021 #define PITTCTRL    0x08
0022 #define PITTFLG     0x0c
0023
0024 #define PITMCR_MDIS (0x1 << 1)
0025
0026 #define PITTCTRL_TEN    (0x1 << 0)
0027 #define PITTCTRL_TIE    (0x1 << 1)
0028 #define PITCTRL_CHN (0x1 << 2)
0029
0030 #define PITTFLG_TIF 0x1
0031
0032 static void __iomem *clksrc_base;
0033 static void __iomem *clkevt_base;
0034 static unsigned long cycle_per_jiffy;
0035
0036 static inline void pit_timer_enable(void)
0037 {
0038     __raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
0039 }
0040
0041 static inline void pit_timer_disable(void)
0042 {
0043     __raw_writel(0, clkevt_base + PITTCTRL);
0044 }
0045
0046 static inline void pit_irq_acknowledge(void)
0047 {
0048     __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
0049 }
0050
0051 static u64 notrace pit_read_sched_clock(void)
0052 {
0053     return ~__raw_readl(clksrc_base + PITCVAL);
0054 }
0055
0056 static int __init pit_clocksource_init(unsigned long rate)
0057 {
0058     /* set the max load value and start the clock source counter */
0059     __raw_writel(0, clksrc_base + PITTCTRL);
0060     __raw_writel(~0UL, clksrc_base + PITLDVAL);
0061     __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
0062
0063     sched_clock_register(pit_read_sched_clock, 32, rate);
0064     return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate,
0065             300, 32, clocksource_mmio_readl_down);
0066 }
0067
0068 static int pit_set_next_event(unsigned long delta,
0069                 struct clock_event_device *unused)
0070 {
0071     /*
0072      * set a new value to PITLDVAL register will not restart the timer,
0073      * to abort the current cycle and start a timer period with the new
0074      * value, the timer must be disabled and enabled again.
0075      * and the PITLAVAL should be set to delta minus one according to pit
0076      * hardware requirement.
0077      */
0078     pit_timer_disable();
0079     __raw_writel(delta - 1, clkevt_base + PITLDVAL);
0080     pit_timer_enable();
0081
0082     return 0;
0083 }
0084
0085 static int pit_shutdown(struct clock_event_device *evt)
0086 {
0087     pit_timer_disable();
0088     return 0;
0089 }
0090
0091 static int pit_set_periodic(struct clock_event_device *evt)
0092 {
0093     pit_set_next_event(cycle_per_jiffy, evt);
0094     return 0;
0095 }
0096
0097 static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
0098 {
0099     struct clock_event_device *evt = dev_id;
0100
0101     pit_irq_acknowledge();
0102
0103     /*
0104      * pit hardware doesn't support oneshot, it will generate an interrupt
0105      * and reload the counter value from PITLDVAL when PITCVAL reach zero,
0106      * and start the counter again. So software need to disable the timer
0107      * to stop the counter loop in ONESHOT mode.
0108      */
0109     if (likely(clockevent_state_oneshot(evt)))
0110         pit_timer_disable();
0111
0112     evt->event_handler(evt);
0113
0114     return IRQ_HANDLED;
0115 }
0116
0117 static struct clock_event_device clockevent_pit = {
0118     .name       = "VF pit timer",
0119     .features   = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
0120     .set_state_shutdown = pit_shutdown,
0121     .set_state_periodic = pit_set_periodic,
0122     .set_next_event = pit_set_next_event,
0123     .rating     = 300,
0124 };
0125
0126 static int __init pit_clockevent_init(unsigned long rate, int irq)
0127 {
0128     __raw_writel(0, clkevt_base + PITTCTRL);
0129     __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
0130
0131     BUG_ON(request_irq(irq, pit_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
0132                "VF pit timer", &clockevent_pit));
0133
0134     clockevent_pit.cpumask = cpumask_of(0);
0135     clockevent_pit.irq = irq;
0136     /*
0137      * The value for the LDVAL register trigger is calculated as:
0138      * LDVAL trigger = (period / clock period) - 1
0139      * The pit is a 32-bit down count timer, when the counter value
0140      * reaches 0, it will generate an interrupt, thus the minimal
0141      * LDVAL trigger value is 1. And then the min_delta is
0142      * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit.
0143      */
0144     clockevents_config_and_register(&clockevent_pit, rate, 2, 0xffffffff);
0145
0146     return 0;
0147 }
0148
0149 static int __init pit_timer_init(struct device_node *np)
0150 {
0151     struct clk *pit_clk;
0152     void __iomem *timer_base;
0153     unsigned long clk_rate;
0154     int irq, ret;
0155
0156     timer_base = of_iomap(np, 0);
0157     if (!timer_base) {
0158         pr_err("Failed to iomap\n");
0159         return -ENXIO;
0160     }
0161
0162     /*
0163      * PIT0 and PIT1 can be chained to build a 64-bit timer,
0164      * so choose PIT2 as clocksource, PIT3 as clockevent device,
0165      * and leave PIT0 and PIT1 unused for anyone else who needs them.
0166      */
0167     clksrc_base = timer_base + PITn_OFFSET(2);
0168     clkevt_base = timer_base + PITn_OFFSET(3);
0169
0170     irq = irq_of_parse_and_map(np, 0);
0171     if (irq <= 0)
0172         return -EINVAL;
0173
0174     pit_clk = of_clk_get(np, 0);
0175     if (IS_ERR(pit_clk))
0176         return PTR_ERR(pit_clk);
0177
0178     ret = clk_prepare_enable(pit_clk);
0179     if (ret)
0180         return ret;
0181
0182     clk_rate = clk_get_rate(pit_clk);
0183     cycle_per_jiffy = clk_rate / (HZ);
0184
0185     /* enable the pit module */
0186     __raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
0187
0188     ret = pit_clocksource_init(clk_rate);
0189     if (ret)
0190         return ret;
0191
0192     return pit_clockevent_init(clk_rate, irq);
0193 }
0194 TIMER_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);