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0001 // SPDX-License-Identifier: GPL-2.0+
0002 #include <linux/clk.h>
0003 #include <linux/clocksource.h>
0004 #include <linux/clockchips.h>
0005 #include <linux/cpuhotplug.h>
0006 #include <linux/interrupt.h>
0007 #include <linux/io.h>
0008 #include <linux/iopoll.h>
0009 #include <linux/err.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <linux/of_irq.h>
0013 #include <linux/sched_clock.h>
0014 
0015 #include <linux/clk/clk-conf.h>
0016 
0017 #include <clocksource/timer-ti-dm.h>
0018 #include <dt-bindings/bus/ti-sysc.h>
0019 
0020 /* For type1, set SYSC_OMAP2_CLOCKACTIVITY for fck off on idle, l4 clock on */
0021 #define DMTIMER_TYPE1_ENABLE    ((1 << 9) | (SYSC_IDLE_SMART << 3) | \
0022                  SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_AUTOIDLE)
0023 #define DMTIMER_TYPE1_DISABLE   (SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)
0024 #define DMTIMER_TYPE2_ENABLE    (SYSC_IDLE_SMART_WKUP << 2)
0025 #define DMTIMER_RESET_WAIT  100000
0026 
0027 #define DMTIMER_INST_DONT_CARE  ~0U
0028 
0029 static int counter_32k;
0030 static u32 clocksource;
0031 static u32 clockevent;
0032 
0033 /*
0034  * Subset of the timer registers we use. Note that the register offsets
0035  * depend on the timer revision detected.
0036  */
0037 struct dmtimer_systimer {
0038     void __iomem *base;
0039     u8 sysc;
0040     u8 irq_stat;
0041     u8 irq_ena;
0042     u8 pend;
0043     u8 load;
0044     u8 counter;
0045     u8 ctrl;
0046     u8 wakeup;
0047     u8 ifctrl;
0048     struct clk *fck;
0049     struct clk *ick;
0050     unsigned long rate;
0051 };
0052 
0053 struct dmtimer_clockevent {
0054     struct clock_event_device dev;
0055     struct dmtimer_systimer t;
0056     u32 period;
0057 };
0058 
0059 struct dmtimer_clocksource {
0060     struct clocksource dev;
0061     struct dmtimer_systimer t;
0062     unsigned int loadval;
0063 };
0064 
0065 /* Assumes v1 ip if bits [31:16] are zero */
0066 static bool dmtimer_systimer_revision1(struct dmtimer_systimer *t)
0067 {
0068     u32 tidr = readl_relaxed(t->base);
0069 
0070     return !(tidr >> 16);
0071 }
0072 
0073 static void dmtimer_systimer_enable(struct dmtimer_systimer *t)
0074 {
0075     u32 val;
0076 
0077     if (dmtimer_systimer_revision1(t))
0078         val = DMTIMER_TYPE1_ENABLE;
0079     else
0080         val = DMTIMER_TYPE2_ENABLE;
0081 
0082     writel_relaxed(val, t->base + t->sysc);
0083 }
0084 
0085 static void dmtimer_systimer_disable(struct dmtimer_systimer *t)
0086 {
0087     if (!dmtimer_systimer_revision1(t))
0088         return;
0089 
0090     writel_relaxed(DMTIMER_TYPE1_DISABLE, t->base + t->sysc);
0091 }
0092 
0093 static int __init dmtimer_systimer_type1_reset(struct dmtimer_systimer *t)
0094 {
0095     void __iomem *syss = t->base + OMAP_TIMER_V1_SYS_STAT_OFFSET;
0096     int ret;
0097     u32 l;
0098 
0099     dmtimer_systimer_enable(t);
0100     writel_relaxed(BIT(1) | BIT(2), t->base + t->ifctrl);
0101     ret = readl_poll_timeout_atomic(syss, l, l & BIT(0), 100,
0102                     DMTIMER_RESET_WAIT);
0103 
0104     return ret;
0105 }
0106 
0107 /* Note we must use io_base instead of func_base for type2 OCP regs */
0108 static int __init dmtimer_systimer_type2_reset(struct dmtimer_systimer *t)
0109 {
0110     void __iomem *sysc = t->base + t->sysc;
0111     u32 l;
0112 
0113     dmtimer_systimer_enable(t);
0114     l = readl_relaxed(sysc);
0115     l |= BIT(0);
0116     writel_relaxed(l, sysc);
0117 
0118     return readl_poll_timeout_atomic(sysc, l, !(l & BIT(0)), 100,
0119                      DMTIMER_RESET_WAIT);
0120 }
0121 
0122 static int __init dmtimer_systimer_reset(struct dmtimer_systimer *t)
0123 {
0124     int ret;
0125 
0126     if (dmtimer_systimer_revision1(t))
0127         ret = dmtimer_systimer_type1_reset(t);
0128     else
0129         ret = dmtimer_systimer_type2_reset(t);
0130     if (ret < 0) {
0131         pr_err("%s failed with %i\n", __func__, ret);
0132 
0133         return ret;
0134     }
0135 
0136     return 0;
0137 }
0138 
0139 static const struct of_device_id counter_match_table[] = {
0140     { .compatible = "ti,omap-counter32k" },
0141     { /* Sentinel */ },
0142 };
0143 
0144 /*
0145  * Check if the SoC als has a usable working 32 KiHz counter. The 32 KiHz
0146  * counter is handled by timer-ti-32k, but we need to detect it as it
0147  * affects the preferred dmtimer system timer configuration. There is
0148  * typically no use for a dmtimer clocksource if the 32 KiHz counter is
0149  * present, except on am437x as described below.
0150  */
0151 static void __init dmtimer_systimer_check_counter32k(void)
0152 {
0153     struct device_node *np;
0154 
0155     if (counter_32k)
0156         return;
0157 
0158     np = of_find_matching_node(NULL, counter_match_table);
0159     if (!np) {
0160         counter_32k = -ENODEV;
0161 
0162         return;
0163     }
0164 
0165     if (of_device_is_available(np))
0166         counter_32k = 1;
0167     else
0168         counter_32k = -ENODEV;
0169 
0170     of_node_put(np);
0171 }
0172 
0173 static const struct of_device_id dmtimer_match_table[] = {
0174     { .compatible = "ti,omap2420-timer", },
0175     { .compatible = "ti,omap3430-timer", },
0176     { .compatible = "ti,omap4430-timer", },
0177     { .compatible = "ti,omap5430-timer", },
0178     { .compatible = "ti,am335x-timer", },
0179     { .compatible = "ti,am335x-timer-1ms", },
0180     { .compatible = "ti,dm814-timer", },
0181     { .compatible = "ti,dm816-timer", },
0182     { /* Sentinel */ },
0183 };
0184 
0185 /*
0186  * Checks that system timers are configured to not reset and idle during
0187  * the generic timer-ti-dm device driver probe. And that the system timer
0188  * source clocks are properly configured. Also, let's not hog any DSP and
0189  * PWM capable timers unnecessarily as system timers.
0190  */
0191 static bool __init dmtimer_is_preferred(struct device_node *np)
0192 {
0193     if (!of_device_is_available(np))
0194         return false;
0195 
0196     if (!of_property_read_bool(np->parent,
0197                    "ti,no-reset-on-init"))
0198         return false;
0199 
0200     if (!of_property_read_bool(np->parent, "ti,no-idle"))
0201         return false;
0202 
0203     /* Secure gptimer12 is always clocked with a fixed source */
0204     if (!of_property_read_bool(np, "ti,timer-secure")) {
0205         if (!of_property_read_bool(np, "assigned-clocks"))
0206             return false;
0207 
0208         if (!of_property_read_bool(np, "assigned-clock-parents"))
0209             return false;
0210     }
0211 
0212     if (of_property_read_bool(np, "ti,timer-dsp"))
0213         return false;
0214 
0215     if (of_property_read_bool(np, "ti,timer-pwm"))
0216         return false;
0217 
0218     return true;
0219 }
0220 
0221 /*
0222  * Finds the first available usable always-on timer, and assigns it to either
0223  * clockevent or clocksource depending if the counter_32k is available on the
0224  * SoC or not.
0225  *
0226  * Some omap3 boards with unreliable oscillator must not use the counter_32k
0227  * or dmtimer1 with 32 KiHz source. Additionally, the boards with unreliable
0228  * oscillator should really set counter_32k as disabled, and delete dmtimer1
0229  * ti,always-on property, but let's not count on it. For these quirky cases,
0230  * we prefer using the always-on secure dmtimer12 with the internal 32 KiHz
0231  * clock as the clocksource, and any available dmtimer as clockevent.
0232  *
0233  * For am437x, we are using am335x style dmtimer clocksource. It is unclear
0234  * if this quirk handling is really needed, but let's change it separately
0235  * based on testing as it might cause side effects.
0236  */
0237 static void __init dmtimer_systimer_assign_alwon(void)
0238 {
0239     struct device_node *np;
0240     u32 pa = 0;
0241     bool quirk_unreliable_oscillator = false;
0242 
0243     /* Quirk unreliable 32 KiHz oscillator with incomplete dts */
0244     if (of_machine_is_compatible("ti,omap3-beagle-ab4")) {
0245         quirk_unreliable_oscillator = true;
0246         counter_32k = -ENODEV;
0247     }
0248 
0249     /* Quirk am437x using am335x style dmtimer clocksource */
0250     if (of_machine_is_compatible("ti,am43"))
0251         counter_32k = -ENODEV;
0252 
0253     for_each_matching_node(np, dmtimer_match_table) {
0254         if (!dmtimer_is_preferred(np))
0255             continue;
0256 
0257         if (of_property_read_bool(np, "ti,timer-alwon")) {
0258             const __be32 *addr;
0259 
0260             addr = of_get_address(np, 0, NULL, NULL);
0261             pa = of_translate_address(np, addr);
0262             if (pa) {
0263                 /* Quirky omap3 boards must use dmtimer12 */
0264                 if (quirk_unreliable_oscillator &&
0265                     pa == 0x48318000)
0266                     continue;
0267 
0268                 of_node_put(np);
0269                 break;
0270             }
0271         }
0272     }
0273 
0274     /* Usually no need for dmtimer clocksource if we have counter32 */
0275     if (counter_32k >= 0) {
0276         clockevent = pa;
0277         clocksource = 0;
0278     } else {
0279         clocksource = pa;
0280         clockevent = DMTIMER_INST_DONT_CARE;
0281     }
0282 }
0283 
0284 /* Finds the first usable dmtimer, used for the don't care case */
0285 static u32 __init dmtimer_systimer_find_first_available(void)
0286 {
0287     struct device_node *np;
0288     const __be32 *addr;
0289     u32 pa = 0;
0290 
0291     for_each_matching_node(np, dmtimer_match_table) {
0292         if (!dmtimer_is_preferred(np))
0293             continue;
0294 
0295         addr = of_get_address(np, 0, NULL, NULL);
0296         pa = of_translate_address(np, addr);
0297         if (pa) {
0298             if (pa == clocksource || pa == clockevent) {
0299                 pa = 0;
0300                 continue;
0301             }
0302 
0303             of_node_put(np);
0304             break;
0305         }
0306     }
0307 
0308     return pa;
0309 }
0310 
0311 /* Selects the best clocksource and clockevent to use */
0312 static void __init dmtimer_systimer_select_best(void)
0313 {
0314     dmtimer_systimer_check_counter32k();
0315     dmtimer_systimer_assign_alwon();
0316 
0317     if (clockevent == DMTIMER_INST_DONT_CARE)
0318         clockevent = dmtimer_systimer_find_first_available();
0319 
0320     pr_debug("%s: counter_32k: %i clocksource: %08x clockevent: %08x\n",
0321          __func__, counter_32k, clocksource, clockevent);
0322 }
0323 
0324 /* Interface clocks are only available on some SoCs variants */
0325 static int __init dmtimer_systimer_init_clock(struct dmtimer_systimer *t,
0326                           struct device_node *np,
0327                           const char *name,
0328                           unsigned long *rate)
0329 {
0330     struct clk *clock;
0331     unsigned long r;
0332     bool is_ick = false;
0333     int error;
0334 
0335     is_ick = !strncmp(name, "ick", 3);
0336 
0337     clock = of_clk_get_by_name(np, name);
0338     if ((PTR_ERR(clock) == -EINVAL) && is_ick)
0339         return 0;
0340     else if (IS_ERR(clock))
0341         return PTR_ERR(clock);
0342 
0343     error = clk_prepare_enable(clock);
0344     if (error)
0345         return error;
0346 
0347     r = clk_get_rate(clock);
0348     if (!r)
0349         return -ENODEV;
0350 
0351     if (is_ick)
0352         t->ick = clock;
0353     else
0354         t->fck = clock;
0355 
0356     *rate = r;
0357 
0358     return 0;
0359 }
0360 
0361 static int __init dmtimer_systimer_setup(struct device_node *np,
0362                      struct dmtimer_systimer *t)
0363 {
0364     unsigned long rate;
0365     u8 regbase;
0366     int error;
0367 
0368     if (!of_device_is_compatible(np->parent, "ti,sysc"))
0369         return -EINVAL;
0370 
0371     t->base = of_iomap(np, 0);
0372     if (!t->base)
0373         return -ENXIO;
0374 
0375     /*
0376      * Enable optional assigned-clock-parents configured at the timer
0377      * node level. For regular device drivers, this is done automatically
0378      * by bus related code such as platform_drv_probe().
0379      */
0380     error = of_clk_set_defaults(np, false);
0381     if (error < 0)
0382         pr_err("%s: clock source init failed: %i\n", __func__, error);
0383 
0384     /* For ti-sysc, we have timer clocks at the parent module level */
0385     error = dmtimer_systimer_init_clock(t, np->parent, "fck", &rate);
0386     if (error)
0387         goto err_unmap;
0388 
0389     t->rate = rate;
0390 
0391     error = dmtimer_systimer_init_clock(t, np->parent, "ick", &rate);
0392     if (error)
0393         goto err_unmap;
0394 
0395     if (dmtimer_systimer_revision1(t)) {
0396         t->irq_stat = OMAP_TIMER_V1_STAT_OFFSET;
0397         t->irq_ena = OMAP_TIMER_V1_INT_EN_OFFSET;
0398         t->pend = _OMAP_TIMER_WRITE_PEND_OFFSET;
0399         regbase = 0;
0400     } else {
0401         t->irq_stat = OMAP_TIMER_V2_IRQSTATUS;
0402         t->irq_ena = OMAP_TIMER_V2_IRQENABLE_SET;
0403         regbase = OMAP_TIMER_V2_FUNC_OFFSET;
0404         t->pend = regbase + _OMAP_TIMER_WRITE_PEND_OFFSET;
0405     }
0406 
0407     t->sysc = OMAP_TIMER_OCP_CFG_OFFSET;
0408     t->load = regbase + _OMAP_TIMER_LOAD_OFFSET;
0409     t->counter = regbase + _OMAP_TIMER_COUNTER_OFFSET;
0410     t->ctrl = regbase + _OMAP_TIMER_CTRL_OFFSET;
0411     t->wakeup = regbase + _OMAP_TIMER_WAKEUP_EN_OFFSET;
0412     t->ifctrl = regbase + _OMAP_TIMER_IF_CTRL_OFFSET;
0413 
0414     dmtimer_systimer_reset(t);
0415     dmtimer_systimer_enable(t);
0416     pr_debug("dmtimer rev %08x sysc %08x\n", readl_relaxed(t->base),
0417          readl_relaxed(t->base + t->sysc));
0418 
0419     return 0;
0420 
0421 err_unmap:
0422     iounmap(t->base);
0423 
0424     return error;
0425 }
0426 
0427 /* Clockevent */
0428 static struct dmtimer_clockevent *
0429 to_dmtimer_clockevent(struct clock_event_device *clockevent)
0430 {
0431     return container_of(clockevent, struct dmtimer_clockevent, dev);
0432 }
0433 
0434 static irqreturn_t dmtimer_clockevent_interrupt(int irq, void *data)
0435 {
0436     struct dmtimer_clockevent *clkevt = data;
0437     struct dmtimer_systimer *t = &clkevt->t;
0438 
0439     writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);
0440     clkevt->dev.event_handler(&clkevt->dev);
0441 
0442     return IRQ_HANDLED;
0443 }
0444 
0445 static int dmtimer_set_next_event(unsigned long cycles,
0446                   struct clock_event_device *evt)
0447 {
0448     struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
0449     struct dmtimer_systimer *t = &clkevt->t;
0450     void __iomem *pend = t->base + t->pend;
0451 
0452     while (readl_relaxed(pend) & WP_TCRR)
0453         cpu_relax();
0454     writel_relaxed(0xffffffff - cycles, t->base + t->counter);
0455 
0456     while (readl_relaxed(pend) & WP_TCLR)
0457         cpu_relax();
0458     writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl);
0459 
0460     return 0;
0461 }
0462 
0463 static int dmtimer_clockevent_shutdown(struct clock_event_device *evt)
0464 {
0465     struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
0466     struct dmtimer_systimer *t = &clkevt->t;
0467     void __iomem *ctrl = t->base + t->ctrl;
0468     u32 l;
0469 
0470     l = readl_relaxed(ctrl);
0471     if (l & OMAP_TIMER_CTRL_ST) {
0472         l &= ~BIT(0);
0473         writel_relaxed(l, ctrl);
0474         /* Flush posted write */
0475         l = readl_relaxed(ctrl);
0476         /*  Wait for functional clock period x 3.5 */
0477         udelay(3500000 / t->rate + 1);
0478     }
0479     writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);
0480 
0481     return 0;
0482 }
0483 
0484 static int dmtimer_set_periodic(struct clock_event_device *evt)
0485 {
0486     struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
0487     struct dmtimer_systimer *t = &clkevt->t;
0488     void __iomem *pend = t->base + t->pend;
0489 
0490     dmtimer_clockevent_shutdown(evt);
0491 
0492     /* Looks like we need to first set the load value separately */
0493     while (readl_relaxed(pend) & WP_TLDR)
0494         cpu_relax();
0495     writel_relaxed(clkevt->period, t->base + t->load);
0496 
0497     while (readl_relaxed(pend) & WP_TCRR)
0498         cpu_relax();
0499     writel_relaxed(clkevt->period, t->base + t->counter);
0500 
0501     while (readl_relaxed(pend) & WP_TCLR)
0502         cpu_relax();
0503     writel_relaxed(OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
0504                t->base + t->ctrl);
0505 
0506     return 0;
0507 }
0508 
0509 static void omap_clockevent_idle(struct clock_event_device *evt)
0510 {
0511     struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
0512     struct dmtimer_systimer *t = &clkevt->t;
0513 
0514     dmtimer_systimer_disable(t);
0515     clk_disable(t->fck);
0516 }
0517 
0518 static void omap_clockevent_unidle(struct clock_event_device *evt)
0519 {
0520     struct dmtimer_clockevent *clkevt = to_dmtimer_clockevent(evt);
0521     struct dmtimer_systimer *t = &clkevt->t;
0522     int error;
0523 
0524     error = clk_enable(t->fck);
0525     if (error)
0526         pr_err("could not enable timer fck on resume: %i\n", error);
0527 
0528     dmtimer_systimer_enable(t);
0529     writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
0530     writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
0531 }
0532 
0533 static int __init dmtimer_clkevt_init_common(struct dmtimer_clockevent *clkevt,
0534                          struct device_node *np,
0535                          unsigned int features,
0536                          const struct cpumask *cpumask,
0537                          const char *name,
0538                          int rating)
0539 {
0540     struct clock_event_device *dev;
0541     struct dmtimer_systimer *t;
0542     int error;
0543 
0544     t = &clkevt->t;
0545     dev = &clkevt->dev;
0546 
0547     /*
0548      * We mostly use cpuidle_coupled with ARM local timers for runtime,
0549      * so there's probably no use for CLOCK_EVT_FEAT_DYNIRQ here.
0550      */
0551     dev->features = features;
0552     dev->rating = rating;
0553     dev->set_next_event = dmtimer_set_next_event;
0554     dev->set_state_shutdown = dmtimer_clockevent_shutdown;
0555     dev->set_state_periodic = dmtimer_set_periodic;
0556     dev->set_state_oneshot = dmtimer_clockevent_shutdown;
0557     dev->set_state_oneshot_stopped = dmtimer_clockevent_shutdown;
0558     dev->tick_resume = dmtimer_clockevent_shutdown;
0559     dev->cpumask = cpumask;
0560 
0561     dev->irq = irq_of_parse_and_map(np, 0);
0562     if (!dev->irq)
0563         return -ENXIO;
0564 
0565     error = dmtimer_systimer_setup(np, &clkevt->t);
0566     if (error)
0567         return error;
0568 
0569     clkevt->period = 0xffffffff - DIV_ROUND_CLOSEST(t->rate, HZ);
0570 
0571     /*
0572      * For clock-event timers we never read the timer counter and
0573      * so we are not impacted by errata i103 and i767. Therefore,
0574      * we can safely ignore this errata for clock-event timers.
0575      */
0576     writel_relaxed(OMAP_TIMER_CTRL_POSTED, t->base + t->ifctrl);
0577 
0578     error = request_irq(dev->irq, dmtimer_clockevent_interrupt,
0579                 IRQF_TIMER, name, clkevt);
0580     if (error)
0581         goto err_out_unmap;
0582 
0583     writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
0584     writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
0585 
0586     pr_info("TI gptimer %s: %s%lu Hz at %pOF\n",
0587         name, of_find_property(np, "ti,timer-alwon", NULL) ?
0588         "always-on " : "", t->rate, np->parent);
0589 
0590     return 0;
0591 
0592 err_out_unmap:
0593     iounmap(t->base);
0594 
0595     return error;
0596 }
0597 
0598 static int __init dmtimer_clockevent_init(struct device_node *np)
0599 {
0600     struct dmtimer_clockevent *clkevt;
0601     int error;
0602 
0603     clkevt = kzalloc(sizeof(*clkevt), GFP_KERNEL);
0604     if (!clkevt)
0605         return -ENOMEM;
0606 
0607     error = dmtimer_clkevt_init_common(clkevt, np,
0608                        CLOCK_EVT_FEAT_PERIODIC |
0609                        CLOCK_EVT_FEAT_ONESHOT,
0610                        cpu_possible_mask, "clockevent",
0611                        300);
0612     if (error)
0613         goto err_out_free;
0614 
0615     clockevents_config_and_register(&clkevt->dev, clkevt->t.rate,
0616                     3, /* Timer internal resync latency */
0617                     0xffffffff);
0618 
0619     if (of_machine_is_compatible("ti,am33xx") ||
0620         of_machine_is_compatible("ti,am43")) {
0621         clkevt->dev.suspend = omap_clockevent_idle;
0622         clkevt->dev.resume = omap_clockevent_unidle;
0623     }
0624 
0625     return 0;
0626 
0627 err_out_free:
0628     kfree(clkevt);
0629 
0630     return error;
0631 }
0632 
0633 /* Dmtimer as percpu timer. See dra7 ARM architected timer wrap erratum i940 */
0634 static DEFINE_PER_CPU(struct dmtimer_clockevent, dmtimer_percpu_timer);
0635 
0636 static int __init dmtimer_percpu_timer_init(struct device_node *np, int cpu)
0637 {
0638     struct dmtimer_clockevent *clkevt;
0639     int error;
0640 
0641     if (!cpu_possible(cpu))
0642         return -EINVAL;
0643 
0644     if (!of_property_read_bool(np->parent, "ti,no-reset-on-init") ||
0645         !of_property_read_bool(np->parent, "ti,no-idle"))
0646         pr_warn("Incomplete dtb for percpu dmtimer %pOF\n", np->parent);
0647 
0648     clkevt = per_cpu_ptr(&dmtimer_percpu_timer, cpu);
0649 
0650     error = dmtimer_clkevt_init_common(clkevt, np, CLOCK_EVT_FEAT_ONESHOT,
0651                        cpumask_of(cpu), "percpu-dmtimer",
0652                        500);
0653     if (error)
0654         return error;
0655 
0656     return 0;
0657 }
0658 
0659 /* See TRM for timer internal resynch latency */
0660 static int omap_dmtimer_starting_cpu(unsigned int cpu)
0661 {
0662     struct dmtimer_clockevent *clkevt = per_cpu_ptr(&dmtimer_percpu_timer, cpu);
0663     struct clock_event_device *dev = &clkevt->dev;
0664     struct dmtimer_systimer *t = &clkevt->t;
0665 
0666     clockevents_config_and_register(dev, t->rate, 3, ULONG_MAX);
0667     irq_force_affinity(dev->irq, cpumask_of(cpu));
0668 
0669     return 0;
0670 }
0671 
0672 static int __init dmtimer_percpu_timer_startup(void)
0673 {
0674     struct dmtimer_clockevent *clkevt = per_cpu_ptr(&dmtimer_percpu_timer, 0);
0675     struct dmtimer_systimer *t = &clkevt->t;
0676 
0677     if (t->sysc) {
0678         cpuhp_setup_state(CPUHP_AP_TI_GP_TIMER_STARTING,
0679                   "clockevents/omap/gptimer:starting",
0680                   omap_dmtimer_starting_cpu, NULL);
0681     }
0682 
0683     return 0;
0684 }
0685 subsys_initcall(dmtimer_percpu_timer_startup);
0686 
0687 static int __init dmtimer_percpu_quirk_init(struct device_node *np, u32 pa)
0688 {
0689     struct device_node *arm_timer;
0690 
0691     arm_timer = of_find_compatible_node(NULL, NULL, "arm,armv7-timer");
0692     if (of_device_is_available(arm_timer)) {
0693         pr_warn_once("ARM architected timer wrap issue i940 detected\n");
0694         return 0;
0695     }
0696 
0697     if (pa == 0x4882c000)           /* dra7 dmtimer15 */
0698         return dmtimer_percpu_timer_init(np, 0);
0699     else if (pa == 0x4882e000)      /* dra7 dmtimer16 */
0700         return dmtimer_percpu_timer_init(np, 1);
0701 
0702     return 0;
0703 }
0704 
0705 /* Clocksource */
0706 static struct dmtimer_clocksource *
0707 to_dmtimer_clocksource(struct clocksource *cs)
0708 {
0709     return container_of(cs, struct dmtimer_clocksource, dev);
0710 }
0711 
0712 static u64 dmtimer_clocksource_read_cycles(struct clocksource *cs)
0713 {
0714     struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs);
0715     struct dmtimer_systimer *t = &clksrc->t;
0716 
0717     return (u64)readl_relaxed(t->base + t->counter);
0718 }
0719 
0720 static void __iomem *dmtimer_sched_clock_counter;
0721 
0722 static u64 notrace dmtimer_read_sched_clock(void)
0723 {
0724     return readl_relaxed(dmtimer_sched_clock_counter);
0725 }
0726 
0727 static void dmtimer_clocksource_suspend(struct clocksource *cs)
0728 {
0729     struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs);
0730     struct dmtimer_systimer *t = &clksrc->t;
0731 
0732     clksrc->loadval = readl_relaxed(t->base + t->counter);
0733     dmtimer_systimer_disable(t);
0734     clk_disable(t->fck);
0735 }
0736 
0737 static void dmtimer_clocksource_resume(struct clocksource *cs)
0738 {
0739     struct dmtimer_clocksource *clksrc = to_dmtimer_clocksource(cs);
0740     struct dmtimer_systimer *t = &clksrc->t;
0741     int error;
0742 
0743     error = clk_enable(t->fck);
0744     if (error)
0745         pr_err("could not enable timer fck on resume: %i\n", error);
0746 
0747     dmtimer_systimer_enable(t);
0748     writel_relaxed(clksrc->loadval, t->base + t->counter);
0749     writel_relaxed(OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
0750                t->base + t->ctrl);
0751 }
0752 
0753 static int __init dmtimer_clocksource_init(struct device_node *np)
0754 {
0755     struct dmtimer_clocksource *clksrc;
0756     struct dmtimer_systimer *t;
0757     struct clocksource *dev;
0758     int error;
0759 
0760     clksrc = kzalloc(sizeof(*clksrc), GFP_KERNEL);
0761     if (!clksrc)
0762         return -ENOMEM;
0763 
0764     dev = &clksrc->dev;
0765     t = &clksrc->t;
0766 
0767     error = dmtimer_systimer_setup(np, t);
0768     if (error)
0769         goto err_out_free;
0770 
0771     dev->name = "dmtimer";
0772     dev->rating = 300;
0773     dev->read = dmtimer_clocksource_read_cycles;
0774     dev->mask = CLOCKSOURCE_MASK(32);
0775     dev->flags = CLOCK_SOURCE_IS_CONTINUOUS;
0776 
0777     /* Unlike for clockevent, legacy code sets suspend only for am4 */
0778     if (of_machine_is_compatible("ti,am43")) {
0779         dev->suspend = dmtimer_clocksource_suspend;
0780         dev->resume = dmtimer_clocksource_resume;
0781     }
0782 
0783     writel_relaxed(0, t->base + t->counter);
0784     writel_relaxed(OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR,
0785                t->base + t->ctrl);
0786 
0787     pr_info("TI gptimer clocksource: %s%pOF\n",
0788         of_find_property(np, "ti,timer-alwon", NULL) ?
0789         "always-on " : "", np->parent);
0790 
0791     if (!dmtimer_sched_clock_counter) {
0792         dmtimer_sched_clock_counter = t->base + t->counter;
0793         sched_clock_register(dmtimer_read_sched_clock, 32, t->rate);
0794     }
0795 
0796     if (clocksource_register_hz(dev, t->rate))
0797         pr_err("Could not register clocksource %pOF\n", np);
0798 
0799     return 0;
0800 
0801 err_out_free:
0802     kfree(clksrc);
0803 
0804     return -ENODEV;
0805 }
0806 
0807 /*
0808  * To detect between a clocksource and clockevent, we assume the device tree
0809  * has no interrupts configured for a clocksource timer.
0810  */
0811 static int __init dmtimer_systimer_init(struct device_node *np)
0812 {
0813     const __be32 *addr;
0814     u32 pa;
0815 
0816     /* One time init for the preferred timer configuration */
0817     if (!clocksource && !clockevent)
0818         dmtimer_systimer_select_best();
0819 
0820     if (!clocksource && !clockevent) {
0821         pr_err("%s: unable to detect system timers, update dtb?\n",
0822                __func__);
0823 
0824         return -EINVAL;
0825     }
0826 
0827     addr = of_get_address(np, 0, NULL, NULL);
0828     pa = of_translate_address(np, addr);
0829     if (!pa)
0830         return -EINVAL;
0831 
0832     if (counter_32k <= 0 && clocksource == pa)
0833         return dmtimer_clocksource_init(np);
0834 
0835     if (clockevent == pa)
0836         return dmtimer_clockevent_init(np);
0837 
0838     if (of_machine_is_compatible("ti,dra7"))
0839         return dmtimer_percpu_quirk_init(np, pa);
0840 
0841     return 0;
0842 }
0843 
0844 TIMER_OF_DECLARE(systimer_omap2, "ti,omap2420-timer", dmtimer_systimer_init);
0845 TIMER_OF_DECLARE(systimer_omap3, "ti,omap3430-timer", dmtimer_systimer_init);
0846 TIMER_OF_DECLARE(systimer_omap4, "ti,omap4430-timer", dmtimer_systimer_init);
0847 TIMER_OF_DECLARE(systimer_omap5, "ti,omap5430-timer", dmtimer_systimer_init);
0848 TIMER_OF_DECLARE(systimer_am33x, "ti,am335x-timer", dmtimer_systimer_init);
0849 TIMER_OF_DECLARE(systimer_am3ms, "ti,am335x-timer-1ms", dmtimer_systimer_init);
0850 TIMER_OF_DECLARE(systimer_dm814, "ti,dm814-timer", dmtimer_systimer_init);
0851 TIMER_OF_DECLARE(systimer_dm816, "ti,dm816-timer", dmtimer_systimer_init);
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