drivers/clocksource/timer-ti-32k.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /**
0003  * timer-ti-32k.c - OMAP2 32k Timer Support
0004  *
0005  * Copyright (C) 2009 Nokia Corporation
0006  *
0007  * Update to use new clocksource/clockevent layers
0008  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
0009  * Copyright (C) 2007 MontaVista Software, Inc.
0010  *
0011  * Original driver:
0012  * Copyright (C) 2005 Nokia Corporation
0013  * Author: Paul Mundt <paul.mundt@nokia.com>
0014  *         Juha Yrjölä <juha.yrjola@nokia.com>
0015  * OMAP Dual-mode timer framework support by Timo Teras
0016  *
0017  * Some parts based off of TI's 24xx code:
0018  *
0019  * Copyright (C) 2004-2009 Texas Instruments, Inc.
0020  *
0021  * Roughly modelled after the OMAP1 MPU timer code.
0022  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
0023  *
0024  * Copyright (C) 2015 Texas Instruments Incorporated - https://www.ti.com
0025  */
0026
0027 #include <linux/clk.h>
0028 #include <linux/init.h>
0029 #include <linux/time.h>
0030 #include <linux/sched_clock.h>
0031 #include <linux/clocksource.h>
0032 #include <linux/of.h>
0033 #include <linux/of_address.h>
0034
0035 /*
0036  * 32KHz clocksource ... always available, on pretty most chips except
0037  * OMAP 730 and 1510.  Other timers could be used as clocksources, with
0038  * higher resolution in free-running counter modes (e.g. 12 MHz xtal),
0039  * but systems won't necessarily want to spend resources that way.
0040  */
0041
0042 #define OMAP2_32KSYNCNT_REV_OFF     0x0
0043 #define OMAP2_32KSYNCNT_REV_SCHEME  (0x3 << 30)
0044 #define OMAP2_32KSYNCNT_CR_OFF_LOW  0x10
0045 #define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30
0046
0047 struct ti_32k {
0048     void __iomem        *base;
0049     void __iomem        *counter;
0050     struct clocksource  cs;
0051 };
0052
0053 static inline struct ti_32k *to_ti_32k(struct clocksource *cs)
0054 {
0055     return container_of(cs, struct ti_32k, cs);
0056 }
0057
0058 static u64 notrace ti_32k_read_cycles(struct clocksource *cs)
0059 {
0060     struct ti_32k *ti = to_ti_32k(cs);
0061
0062     return (u64)readl_relaxed(ti->counter);
0063 }
0064
0065 static struct ti_32k ti_32k_timer = {
0066     .cs = {
0067         .name       = "32k_counter",
0068         .rating     = 250,
0069         .read       = ti_32k_read_cycles,
0070         .mask       = CLOCKSOURCE_MASK(32),
0071         .flags      = CLOCK_SOURCE_IS_CONTINUOUS,
0072     },
0073 };
0074
0075 static u64 notrace omap_32k_read_sched_clock(void)
0076 {
0077     return ti_32k_read_cycles(&ti_32k_timer.cs);
0078 }
0079
0080 static void __init ti_32k_timer_enable_clock(struct device_node *np,
0081                          const char *name)
0082 {
0083     struct clk *clock;
0084     int error;
0085
0086     clock = of_clk_get_by_name(np->parent, name);
0087     if (IS_ERR(clock)) {
0088         /* Only some SoCs have a separate interface clock */
0089         if (PTR_ERR(clock) == -EINVAL && !strncmp("ick", name, 3))
0090             return;
0091
0092         pr_warn("%s: could not get clock %s %li\n",
0093             __func__, name, PTR_ERR(clock));
0094         return;
0095     }
0096
0097     error = clk_prepare_enable(clock);
0098     if (error) {
0099         pr_warn("%s: could not enable %s: %i\n",
0100             __func__, name, error);
0101         return;
0102     }
0103 }
0104
0105 static void __init ti_32k_timer_module_init(struct device_node *np,
0106                         void __iomem *base)
0107 {
0108     void __iomem *sysc = base + 4;
0109
0110     if (!of_device_is_compatible(np->parent, "ti,sysc"))
0111         return;
0112
0113     ti_32k_timer_enable_clock(np, "fck");
0114     ti_32k_timer_enable_clock(np, "ick");
0115
0116     /*
0117      * Force idle module as wkup domain is active with MPU.
0118      * No need to tag the module disabled for ti-sysc probe.
0119      */
0120     writel_relaxed(0, sysc);
0121 }
0122
0123 static int __init ti_32k_timer_init(struct device_node *np)
0124 {
0125     int ret;
0126
0127     ti_32k_timer.base = of_iomap(np, 0);
0128     if (!ti_32k_timer.base) {
0129         pr_err("Can't ioremap 32k timer base\n");
0130         return -ENXIO;
0131     }
0132
0133     if (!of_machine_is_compatible("ti,am43"))
0134         ti_32k_timer.cs.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
0135
0136     ti_32k_timer.counter = ti_32k_timer.base;
0137     ti_32k_timer_module_init(np, ti_32k_timer.base);
0138
0139     /*
0140      * 32k sync Counter IP register offsets vary between the highlander
0141      * version and the legacy ones.
0142      *
0143      * The 'SCHEME' bits(30-31) of the revision register is used to identify
0144      * the version.
0145      */
0146     if (readl_relaxed(ti_32k_timer.base + OMAP2_32KSYNCNT_REV_OFF) &
0147             OMAP2_32KSYNCNT_REV_SCHEME)
0148         ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_HIGH;
0149     else
0150         ti_32k_timer.counter += OMAP2_32KSYNCNT_CR_OFF_LOW;
0151
0152     pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n");
0153
0154     ret = clocksource_register_hz(&ti_32k_timer.cs, 32768);
0155     if (ret) {
0156         pr_err("32k_counter: can't register clocksource\n");
0157         return ret;
0158     }
0159
0160     sched_clock_register(omap_32k_read_sched_clock, 32, 32768);
0161
0162     return 0;
0163 }
0164 TIMER_OF_DECLARE(ti_32k_timer, "ti,omap-counter32k",
0165         ti_32k_timer_init);