drivers/clocksource/timer-tegra.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2010 Google, Inc.
0004  *
0005  * Author:
0006  *  Colin Cross <ccross@google.com>
0007  */
0008
0009 #define pr_fmt(fmt) "tegra-timer: " fmt
0010
0011 #include <linux/clk.h>
0012 #include <linux/clockchips.h>
0013 #include <linux/cpu.h>
0014 #include <linux/cpumask.h>
0015 #include <linux/delay.h>
0016 #include <linux/err.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/of_address.h>
0019 #include <linux/of_irq.h>
0020 #include <linux/percpu.h>
0021 #include <linux/sched_clock.h>
0022 #include <linux/time.h>
0023
0024 #include "timer-of.h"
0025
0026 #define RTC_SECONDS     0x08
0027 #define RTC_SHADOW_SECONDS  0x0c
0028 #define RTC_MILLISECONDS    0x10
0029
0030 #define TIMERUS_CNTR_1US    0x10
0031 #define TIMERUS_USEC_CFG    0x14
0032 #define TIMERUS_CNTR_FREEZE 0x4c
0033
0034 #define TIMER_PTV       0x0
0035 #define TIMER_PTV_EN        BIT(31)
0036 #define TIMER_PTV_PER       BIT(30)
0037 #define TIMER_PCR       0x4
0038 #define TIMER_PCR_INTR_CLR  BIT(30)
0039
0040 #define TIMER1_BASE     0x00
0041 #define TIMER2_BASE     0x08
0042 #define TIMER3_BASE     0x50
0043 #define TIMER4_BASE     0x58
0044 #define TIMER10_BASE        0x90
0045
0046 #define TIMER1_IRQ_IDX      0
0047 #define TIMER10_IRQ_IDX     10
0048
0049 #define TIMER_1MHz      1000000
0050
0051 static u32 usec_config;
0052 static void __iomem *timer_reg_base;
0053
0054 static int tegra_timer_set_next_event(unsigned long cycles,
0055                       struct clock_event_device *evt)
0056 {
0057     void __iomem *reg_base = timer_of_base(to_timer_of(evt));
0058
0059     /*
0060      * Tegra's timer uses n+1 scheme for the counter, i.e. timer will
0061      * fire after one tick if 0 is loaded.
0062      *
0063      * The minimum and maximum numbers of oneshot ticks are defined
0064      * by clockevents_config_and_register(1, 0x1fffffff + 1) invocation
0065      * below in the code. Hence the cycles (ticks) can't be outside of
0066      * a range supportable by hardware.
0067      */
0068     writel_relaxed(TIMER_PTV_EN | (cycles - 1), reg_base + TIMER_PTV);
0069
0070     return 0;
0071 }
0072
0073 static int tegra_timer_shutdown(struct clock_event_device *evt)
0074 {
0075     void __iomem *reg_base = timer_of_base(to_timer_of(evt));
0076
0077     writel_relaxed(0, reg_base + TIMER_PTV);
0078
0079     return 0;
0080 }
0081
0082 static int tegra_timer_set_periodic(struct clock_event_device *evt)
0083 {
0084     void __iomem *reg_base = timer_of_base(to_timer_of(evt));
0085     unsigned long period = timer_of_period(to_timer_of(evt));
0086
0087     writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1),
0088                reg_base + TIMER_PTV);
0089
0090     return 0;
0091 }
0092
0093 static irqreturn_t tegra_timer_isr(int irq, void *dev_id)
0094 {
0095     struct clock_event_device *evt = dev_id;
0096     void __iomem *reg_base = timer_of_base(to_timer_of(evt));
0097
0098     writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
0099     evt->event_handler(evt);
0100
0101     return IRQ_HANDLED;
0102 }
0103
0104 static void tegra_timer_suspend(struct clock_event_device *evt)
0105 {
0106     void __iomem *reg_base = timer_of_base(to_timer_of(evt));
0107
0108     writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR);
0109 }
0110
0111 static void tegra_timer_resume(struct clock_event_device *evt)
0112 {
0113     writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
0114 }
0115
0116 static DEFINE_PER_CPU(struct timer_of, tegra_to) = {
0117     .flags = TIMER_OF_CLOCK | TIMER_OF_BASE,
0118
0119     .clkevt = {
0120         .name = "tegra_timer",
0121         .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
0122         .set_next_event = tegra_timer_set_next_event,
0123         .set_state_shutdown = tegra_timer_shutdown,
0124         .set_state_periodic = tegra_timer_set_periodic,
0125         .set_state_oneshot = tegra_timer_shutdown,
0126         .tick_resume = tegra_timer_shutdown,
0127         .suspend = tegra_timer_suspend,
0128         .resume = tegra_timer_resume,
0129     },
0130 };
0131
0132 static int tegra_timer_setup(unsigned int cpu)
0133 {
0134     struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
0135
0136     writel_relaxed(0, timer_of_base(to) + TIMER_PTV);
0137     writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR);
0138
0139     irq_force_affinity(to->clkevt.irq, cpumask_of(cpu));
0140     enable_irq(to->clkevt.irq);
0141
0142     /*
0143      * Tegra's timer uses n+1 scheme for the counter, i.e. timer will
0144      * fire after one tick if 0 is loaded and thus minimum number of
0145      * ticks is 1. In result both of the clocksource's tick limits are
0146      * higher than a minimum and maximum that hardware register can
0147      * take by 1, this is then taken into account by set_next_event
0148      * callback.
0149      */
0150     clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
0151                     1, /* min */
0152                     0x1fffffff + 1); /* max 29 bits + 1 */
0153
0154     return 0;
0155 }
0156
0157 static int tegra_timer_stop(unsigned int cpu)
0158 {
0159     struct timer_of *to = per_cpu_ptr(&tegra_to, cpu);
0160
0161     to->clkevt.set_state_shutdown(&to->clkevt);
0162     disable_irq_nosync(to->clkevt.irq);
0163
0164     return 0;
0165 }
0166
0167 static u64 notrace tegra_read_sched_clock(void)
0168 {
0169     return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US);
0170 }
0171
0172 #ifdef CONFIG_ARM
0173 static unsigned long tegra_delay_timer_read_counter_long(void)
0174 {
0175     return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US);
0176 }
0177
0178 static struct delay_timer tegra_delay_timer = {
0179     .read_current_timer = tegra_delay_timer_read_counter_long,
0180     .freq = TIMER_1MHz,
0181 };
0182 #endif
0183
0184 static struct timer_of suspend_rtc_to = {
0185     .flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
0186 };
0187
0188 /*
0189  * tegra_rtc_read - Reads the Tegra RTC registers
0190  * Care must be taken that this function is not called while the
0191  * tegra_rtc driver could be executing to avoid race conditions
0192  * on the RTC shadow register
0193  */
0194 static u64 tegra_rtc_read_ms(struct clocksource *cs)
0195 {
0196     void __iomem *reg_base = timer_of_base(&suspend_rtc_to);
0197
0198     u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS);
0199     u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS);
0200
0201     return (u64)s * MSEC_PER_SEC + ms;
0202 }
0203
0204 static struct clocksource suspend_rtc_clocksource = {
0205     .name   = "tegra_suspend_timer",
0206     .rating = 200,
0207     .read   = tegra_rtc_read_ms,
0208     .mask   = CLOCKSOURCE_MASK(32),
0209     .flags  = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
0210 };
0211
0212 static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20)
0213 {
0214     if (tegra20) {
0215         switch (cpu) {
0216         case 0:
0217             return TIMER1_BASE;
0218         case 1:
0219             return TIMER2_BASE;
0220         case 2:
0221             return TIMER3_BASE;
0222         default:
0223             return TIMER4_BASE;
0224         }
0225     }
0226
0227     return TIMER10_BASE + cpu * 8;
0228 }
0229
0230 static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20)
0231 {
0232     if (tegra20)
0233         return TIMER1_IRQ_IDX + cpu;
0234
0235     return TIMER10_IRQ_IDX + cpu;
0236 }
0237
0238 static inline unsigned long tegra_rate_for_timer(struct timer_of *to,
0239                          bool tegra20)
0240 {
0241     /*
0242      * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the
0243      * parent clock.
0244      */
0245     if (tegra20)
0246         return TIMER_1MHz;
0247
0248     return timer_of_rate(to);
0249 }
0250
0251 static int __init tegra_init_timer(struct device_node *np, bool tegra20,
0252                    int rating)
0253 {
0254     struct timer_of *to;
0255     int cpu, ret;
0256
0257     to = this_cpu_ptr(&tegra_to);
0258     ret = timer_of_init(np, to);
0259     if (ret)
0260         goto out;
0261
0262     timer_reg_base = timer_of_base(to);
0263
0264     /*
0265      * Configure microsecond timers to have 1MHz clock
0266      * Config register is 0xqqww, where qq is "dividend", ww is "divisor"
0267      * Uses n+1 scheme
0268      */
0269     switch (timer_of_rate(to)) {
0270     case 12000000:
0271         usec_config = 0x000b; /* (11+1)/(0+1) */
0272         break;
0273     case 12800000:
0274         usec_config = 0x043f; /* (63+1)/(4+1) */
0275         break;
0276     case 13000000:
0277         usec_config = 0x000c; /* (12+1)/(0+1) */
0278         break;
0279     case 16800000:
0280         usec_config = 0x0453; /* (83+1)/(4+1) */
0281         break;
0282     case 19200000:
0283         usec_config = 0x045f; /* (95+1)/(4+1) */
0284         break;
0285     case 26000000:
0286         usec_config = 0x0019; /* (25+1)/(0+1) */
0287         break;
0288     case 38400000:
0289         usec_config = 0x04bf; /* (191+1)/(4+1) */
0290         break;
0291     case 48000000:
0292         usec_config = 0x002f; /* (47+1)/(0+1) */
0293         break;
0294     default:
0295         ret = -EINVAL;
0296         goto out;
0297     }
0298
0299     writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
0300
0301     for_each_possible_cpu(cpu) {
0302         struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu);
0303         unsigned long flags = IRQF_TIMER | IRQF_NOBALANCING;
0304         unsigned long rate = tegra_rate_for_timer(to, tegra20);
0305         unsigned int base = tegra_base_for_cpu(cpu, tegra20);
0306         unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20);
0307         unsigned int irq = irq_of_parse_and_map(np, idx);
0308
0309         if (!irq) {
0310             pr_err("failed to map irq for cpu%d\n", cpu);
0311             ret = -EINVAL;
0312             goto out_irq;
0313         }
0314
0315         cpu_to->clkevt.irq = irq;
0316         cpu_to->clkevt.rating = rating;
0317         cpu_to->clkevt.cpumask = cpumask_of(cpu);
0318         cpu_to->of_base.base = timer_reg_base + base;
0319         cpu_to->of_clk.period = rate / HZ;
0320         cpu_to->of_clk.rate = rate;
0321
0322         irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
0323
0324         ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, flags,
0325                   cpu_to->clkevt.name, &cpu_to->clkevt);
0326         if (ret) {
0327             pr_err("failed to set up irq for cpu%d: %d\n",
0328                    cpu, ret);
0329             irq_dispose_mapping(cpu_to->clkevt.irq);
0330             cpu_to->clkevt.irq = 0;
0331             goto out_irq;
0332         }
0333     }
0334
0335     sched_clock_register(tegra_read_sched_clock, 32, TIMER_1MHz);
0336
0337     ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
0338                     "timer_us", TIMER_1MHz, 300, 32,
0339                     clocksource_mmio_readl_up);
0340     if (ret)
0341         pr_err("failed to register clocksource: %d\n", ret);
0342
0343 #ifdef CONFIG_ARM
0344     register_current_timer_delay(&tegra_delay_timer);
0345 #endif
0346
0347     ret = cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
0348                 "AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
0349                 tegra_timer_stop);
0350     if (ret)
0351         pr_err("failed to set up cpu hp state: %d\n", ret);
0352
0353     return ret;
0354
0355 out_irq:
0356     for_each_possible_cpu(cpu) {
0357         struct timer_of *cpu_to;
0358
0359         cpu_to = per_cpu_ptr(&tegra_to, cpu);
0360         if (cpu_to->clkevt.irq) {
0361             free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
0362             irq_dispose_mapping(cpu_to->clkevt.irq);
0363         }
0364     }
0365
0366     to->of_base.base = timer_reg_base;
0367 out:
0368     timer_of_cleanup(to);
0369
0370     return ret;
0371 }
0372
0373 static int __init tegra210_init_timer(struct device_node *np)
0374 {
0375     /*
0376      * Arch-timer can't survive across power cycle of CPU core and
0377      * after CPUPORESET signal due to a system design shortcoming,
0378      * hence tegra-timer is more preferable on Tegra210.
0379      */
0380     return tegra_init_timer(np, false, 460);
0381 }
0382 TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer);
0383
0384 static int __init tegra20_init_timer(struct device_node *np)
0385 {
0386     int rating;
0387
0388     /*
0389      * Tegra20 and Tegra30 have Cortex A9 CPU that has a TWD timer,
0390      * that timer runs off the CPU clock and hence is subjected to
0391      * a jitter caused by DVFS clock rate changes. Tegra-timer is
0392      * more preferable for older Tegra's, while later SoC generations
0393      * have arch-timer as a main per-CPU timer and it is not affected
0394      * by DVFS changes.
0395      */
0396     if (of_machine_is_compatible("nvidia,tegra20") ||
0397         of_machine_is_compatible("nvidia,tegra30"))
0398         rating = 460;
0399     else
0400         rating = 330;
0401
0402     return tegra_init_timer(np, true, rating);
0403 }
0404 TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
0405
0406 static int __init tegra20_init_rtc(struct device_node *np)
0407 {
0408     int ret;
0409
0410     ret = timer_of_init(np, &suspend_rtc_to);
0411     if (ret)
0412         return ret;
0413
0414     return clocksource_register_hz(&suspend_rtc_clocksource, 1000);
0415 }
0416 TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);