drivers/clocksource/timer-stm32-lp.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
0004  * Authors: Benjamin Gaignard <benjamin.gaignard@st.com> for STMicroelectronics.
0005  *      Pascal Paillet <p.paillet@st.com> for STMicroelectronics.
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/clockchips.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/mfd/stm32-lptimer.h>
0012 #include <linux/module.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_irq.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/pm_wakeirq.h>
0017
0018 #define CFGR_PSC_OFFSET     9
0019 #define STM32_LP_RATING     1000
0020 #define STM32_TARGET_CLKRATE    (32000 * HZ)
0021 #define STM32_LP_MAX_PSC    7
0022
0023 struct stm32_lp_private {
0024     struct regmap *reg;
0025     struct clock_event_device clkevt;
0026     unsigned long period;
0027     struct device *dev;
0028 };
0029
0030 static struct stm32_lp_private*
0031 to_priv(struct clock_event_device *clkevt)
0032 {
0033     return container_of(clkevt, struct stm32_lp_private, clkevt);
0034 }
0035
0036 static int stm32_clkevent_lp_shutdown(struct clock_event_device *clkevt)
0037 {
0038     struct stm32_lp_private *priv = to_priv(clkevt);
0039
0040     regmap_write(priv->reg, STM32_LPTIM_CR, 0);
0041     regmap_write(priv->reg, STM32_LPTIM_IER, 0);
0042     /* clear pending flags */
0043     regmap_write(priv->reg, STM32_LPTIM_ICR, STM32_LPTIM_ARRMCF);
0044
0045     return 0;
0046 }
0047
0048 static int stm32_clkevent_lp_set_timer(unsigned long evt,
0049                        struct clock_event_device *clkevt,
0050                        int is_periodic)
0051 {
0052     struct stm32_lp_private *priv = to_priv(clkevt);
0053
0054     /* disable LPTIMER to be able to write into IER register*/
0055     regmap_write(priv->reg, STM32_LPTIM_CR, 0);
0056     /* enable ARR interrupt */
0057     regmap_write(priv->reg, STM32_LPTIM_IER, STM32_LPTIM_ARRMIE);
0058     /* enable LPTIMER to be able to write into ARR register */
0059     regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE);
0060     /* set next event counter */
0061     regmap_write(priv->reg, STM32_LPTIM_ARR, evt);
0062
0063     /* start counter */
0064     if (is_periodic)
0065         regmap_write(priv->reg, STM32_LPTIM_CR,
0066                  STM32_LPTIM_CNTSTRT | STM32_LPTIM_ENABLE);
0067     else
0068         regmap_write(priv->reg, STM32_LPTIM_CR,
0069                  STM32_LPTIM_SNGSTRT | STM32_LPTIM_ENABLE);
0070
0071     return 0;
0072 }
0073
0074 static int stm32_clkevent_lp_set_next_event(unsigned long evt,
0075                         struct clock_event_device *clkevt)
0076 {
0077     return stm32_clkevent_lp_set_timer(evt, clkevt,
0078                        clockevent_state_periodic(clkevt));
0079 }
0080
0081 static int stm32_clkevent_lp_set_periodic(struct clock_event_device *clkevt)
0082 {
0083     struct stm32_lp_private *priv = to_priv(clkevt);
0084
0085     return stm32_clkevent_lp_set_timer(priv->period, clkevt, true);
0086 }
0087
0088 static int stm32_clkevent_lp_set_oneshot(struct clock_event_device *clkevt)
0089 {
0090     struct stm32_lp_private *priv = to_priv(clkevt);
0091
0092     return stm32_clkevent_lp_set_timer(priv->period, clkevt, false);
0093 }
0094
0095 static irqreturn_t stm32_clkevent_lp_irq_handler(int irq, void *dev_id)
0096 {
0097     struct clock_event_device *clkevt = (struct clock_event_device *)dev_id;
0098     struct stm32_lp_private *priv = to_priv(clkevt);
0099
0100     regmap_write(priv->reg, STM32_LPTIM_ICR, STM32_LPTIM_ARRMCF);
0101
0102     if (clkevt->event_handler)
0103         clkevt->event_handler(clkevt);
0104
0105     return IRQ_HANDLED;
0106 }
0107
0108 static void stm32_clkevent_lp_set_prescaler(struct stm32_lp_private *priv,
0109                         unsigned long *rate)
0110 {
0111     int i;
0112
0113     for (i = 0; i <= STM32_LP_MAX_PSC; i++) {
0114         if (DIV_ROUND_CLOSEST(*rate, 1 << i) < STM32_TARGET_CLKRATE)
0115             break;
0116     }
0117
0118     regmap_write(priv->reg, STM32_LPTIM_CFGR, i << CFGR_PSC_OFFSET);
0119
0120     /* Adjust rate and period given the prescaler value */
0121     *rate = DIV_ROUND_CLOSEST(*rate, (1 << i));
0122     priv->period = DIV_ROUND_UP(*rate, HZ);
0123 }
0124
0125 static void stm32_clkevent_lp_init(struct stm32_lp_private *priv,
0126                   struct device_node *np, unsigned long rate)
0127 {
0128     priv->clkevt.name = np->full_name;
0129     priv->clkevt.cpumask = cpu_possible_mask;
0130     priv->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
0131                 CLOCK_EVT_FEAT_ONESHOT;
0132     priv->clkevt.set_state_shutdown = stm32_clkevent_lp_shutdown;
0133     priv->clkevt.set_state_periodic = stm32_clkevent_lp_set_periodic;
0134     priv->clkevt.set_state_oneshot = stm32_clkevent_lp_set_oneshot;
0135     priv->clkevt.set_next_event = stm32_clkevent_lp_set_next_event;
0136     priv->clkevt.rating = STM32_LP_RATING;
0137
0138     clockevents_config_and_register(&priv->clkevt, rate, 0x1,
0139                     STM32_LPTIM_MAX_ARR);
0140 }
0141
0142 static int stm32_clkevent_lp_probe(struct platform_device *pdev)
0143 {
0144     struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
0145     struct stm32_lp_private *priv;
0146     unsigned long rate;
0147     int ret, irq;
0148
0149     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0150     if (!priv)
0151         return -ENOMEM;
0152
0153     priv->reg = ddata->regmap;
0154     ret = clk_prepare_enable(ddata->clk);
0155     if (ret)
0156         return -EINVAL;
0157
0158     rate = clk_get_rate(ddata->clk);
0159     if (!rate) {
0160         ret = -EINVAL;
0161         goto out_clk_disable;
0162     }
0163
0164     irq = platform_get_irq(to_platform_device(pdev->dev.parent), 0);
0165     if (irq <= 0) {
0166         ret = irq;
0167         goto out_clk_disable;
0168     }
0169
0170     if (of_property_read_bool(pdev->dev.parent->of_node, "wakeup-source")) {
0171         ret = device_init_wakeup(&pdev->dev, true);
0172         if (ret)
0173             goto out_clk_disable;
0174
0175         ret = dev_pm_set_wake_irq(&pdev->dev, irq);
0176         if (ret)
0177             goto out_clk_disable;
0178     }
0179
0180     ret = devm_request_irq(&pdev->dev, irq, stm32_clkevent_lp_irq_handler,
0181                    IRQF_TIMER, pdev->name, &priv->clkevt);
0182     if (ret)
0183         goto out_clk_disable;
0184
0185     stm32_clkevent_lp_set_prescaler(priv, &rate);
0186
0187     stm32_clkevent_lp_init(priv, pdev->dev.parent->of_node, rate);
0188
0189     priv->dev = &pdev->dev;
0190
0191     return 0;
0192
0193 out_clk_disable:
0194     clk_disable_unprepare(ddata->clk);
0195     return ret;
0196 }
0197
0198 static int stm32_clkevent_lp_remove(struct platform_device *pdev)
0199 {
0200     return -EBUSY; /* cannot unregister clockevent */
0201 }
0202
0203 static const struct of_device_id stm32_clkevent_lp_of_match[] = {
0204     { .compatible = "st,stm32-lptimer-timer", },
0205     {},
0206 };
0207 MODULE_DEVICE_TABLE(of, stm32_clkevent_lp_of_match);
0208
0209 static struct platform_driver stm32_clkevent_lp_driver = {
0210     .probe  = stm32_clkevent_lp_probe,
0211     .remove = stm32_clkevent_lp_remove,
0212     .driver = {
0213         .name = "stm32-lptimer-timer",
0214         .of_match_table = of_match_ptr(stm32_clkevent_lp_of_match),
0215     },
0216 };
0217 module_platform_driver(stm32_clkevent_lp_driver);
0218
0219 MODULE_ALIAS("platform:stm32-lptimer-timer");
0220 MODULE_DESCRIPTION("STMicroelectronics STM32 clockevent low power driver");
0221 MODULE_LICENSE("GPL v2");