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0006 #include <linux/init.h>
0007 #include <linux/interrupt.h>
0008
0009 #include "timer-of.h"
0010
0011 #define TIMER_NAME "sprd_timer"
0012
0013 #define TIMER_LOAD_LO 0x0
0014 #define TIMER_LOAD_HI 0x4
0015 #define TIMER_VALUE_LO 0x8
0016 #define TIMER_VALUE_HI 0xc
0017
0018 #define TIMER_CTL 0x10
0019 #define TIMER_CTL_PERIOD_MODE BIT(0)
0020 #define TIMER_CTL_ENABLE BIT(1)
0021 #define TIMER_CTL_64BIT_WIDTH BIT(16)
0022
0023 #define TIMER_INT 0x14
0024 #define TIMER_INT_EN BIT(0)
0025 #define TIMER_INT_RAW_STS BIT(1)
0026 #define TIMER_INT_MASK_STS BIT(2)
0027 #define TIMER_INT_CLR BIT(3)
0028
0029 #define TIMER_VALUE_SHDW_LO 0x18
0030 #define TIMER_VALUE_SHDW_HI 0x1c
0031
0032 #define TIMER_VALUE_LO_MASK GENMASK(31, 0)
0033
0034 static void sprd_timer_enable(void __iomem *base, u32 flag)
0035 {
0036 u32 val = readl_relaxed(base + TIMER_CTL);
0037
0038 val |= TIMER_CTL_ENABLE;
0039 if (flag & TIMER_CTL_64BIT_WIDTH)
0040 val |= TIMER_CTL_64BIT_WIDTH;
0041 else
0042 val &= ~TIMER_CTL_64BIT_WIDTH;
0043
0044 if (flag & TIMER_CTL_PERIOD_MODE)
0045 val |= TIMER_CTL_PERIOD_MODE;
0046 else
0047 val &= ~TIMER_CTL_PERIOD_MODE;
0048
0049 writel_relaxed(val, base + TIMER_CTL);
0050 }
0051
0052 static void sprd_timer_disable(void __iomem *base)
0053 {
0054 u32 val = readl_relaxed(base + TIMER_CTL);
0055
0056 val &= ~TIMER_CTL_ENABLE;
0057 writel_relaxed(val, base + TIMER_CTL);
0058 }
0059
0060 static void sprd_timer_update_counter(void __iomem *base, unsigned long cycles)
0061 {
0062 writel_relaxed(cycles & TIMER_VALUE_LO_MASK, base + TIMER_LOAD_LO);
0063 writel_relaxed(0, base + TIMER_LOAD_HI);
0064 }
0065
0066 static void sprd_timer_enable_interrupt(void __iomem *base)
0067 {
0068 writel_relaxed(TIMER_INT_EN, base + TIMER_INT);
0069 }
0070
0071 static void sprd_timer_clear_interrupt(void __iomem *base)
0072 {
0073 u32 val = readl_relaxed(base + TIMER_INT);
0074
0075 val |= TIMER_INT_CLR;
0076 writel_relaxed(val, base + TIMER_INT);
0077 }
0078
0079 static int sprd_timer_set_next_event(unsigned long cycles,
0080 struct clock_event_device *ce)
0081 {
0082 struct timer_of *to = to_timer_of(ce);
0083
0084 sprd_timer_disable(timer_of_base(to));
0085 sprd_timer_update_counter(timer_of_base(to), cycles);
0086 sprd_timer_enable(timer_of_base(to), 0);
0087
0088 return 0;
0089 }
0090
0091 static int sprd_timer_set_periodic(struct clock_event_device *ce)
0092 {
0093 struct timer_of *to = to_timer_of(ce);
0094
0095 sprd_timer_disable(timer_of_base(to));
0096 sprd_timer_update_counter(timer_of_base(to), timer_of_period(to));
0097 sprd_timer_enable(timer_of_base(to), TIMER_CTL_PERIOD_MODE);
0098
0099 return 0;
0100 }
0101
0102 static int sprd_timer_shutdown(struct clock_event_device *ce)
0103 {
0104 struct timer_of *to = to_timer_of(ce);
0105
0106 sprd_timer_disable(timer_of_base(to));
0107 return 0;
0108 }
0109
0110 static irqreturn_t sprd_timer_interrupt(int irq, void *dev_id)
0111 {
0112 struct clock_event_device *ce = (struct clock_event_device *)dev_id;
0113 struct timer_of *to = to_timer_of(ce);
0114
0115 sprd_timer_clear_interrupt(timer_of_base(to));
0116
0117 if (clockevent_state_oneshot(ce))
0118 sprd_timer_disable(timer_of_base(to));
0119
0120 ce->event_handler(ce);
0121 return IRQ_HANDLED;
0122 }
0123
0124 static struct timer_of to = {
0125 .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
0126
0127 .clkevt = {
0128 .name = TIMER_NAME,
0129 .rating = 300,
0130 .features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_PERIODIC |
0131 CLOCK_EVT_FEAT_ONESHOT,
0132 .set_state_shutdown = sprd_timer_shutdown,
0133 .set_state_periodic = sprd_timer_set_periodic,
0134 .set_next_event = sprd_timer_set_next_event,
0135 .cpumask = cpu_possible_mask,
0136 },
0137
0138 .of_irq = {
0139 .handler = sprd_timer_interrupt,
0140 .flags = IRQF_TIMER | IRQF_IRQPOLL,
0141 },
0142 };
0143
0144 static int __init sprd_timer_init(struct device_node *np)
0145 {
0146 int ret;
0147
0148 ret = timer_of_init(np, &to);
0149 if (ret)
0150 return ret;
0151
0152 sprd_timer_enable_interrupt(timer_of_base(&to));
0153 clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
0154 1, UINT_MAX);
0155
0156 return 0;
0157 }
0158
0159 static struct timer_of suspend_to = {
0160 .flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
0161 };
0162
0163 static u64 sprd_suspend_timer_read(struct clocksource *cs)
0164 {
0165 return ~(u64)readl_relaxed(timer_of_base(&suspend_to) +
0166 TIMER_VALUE_SHDW_LO) & cs->mask;
0167 }
0168
0169 static int sprd_suspend_timer_enable(struct clocksource *cs)
0170 {
0171 sprd_timer_update_counter(timer_of_base(&suspend_to),
0172 TIMER_VALUE_LO_MASK);
0173 sprd_timer_enable(timer_of_base(&suspend_to), TIMER_CTL_PERIOD_MODE);
0174
0175 return 0;
0176 }
0177
0178 static void sprd_suspend_timer_disable(struct clocksource *cs)
0179 {
0180 sprd_timer_disable(timer_of_base(&suspend_to));
0181 }
0182
0183 static struct clocksource suspend_clocksource = {
0184 .name = "sprd_suspend_timer",
0185 .rating = 200,
0186 .read = sprd_suspend_timer_read,
0187 .enable = sprd_suspend_timer_enable,
0188 .disable = sprd_suspend_timer_disable,
0189 .mask = CLOCKSOURCE_MASK(32),
0190 .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
0191 };
0192
0193 static int __init sprd_suspend_timer_init(struct device_node *np)
0194 {
0195 int ret;
0196
0197 ret = timer_of_init(np, &suspend_to);
0198 if (ret)
0199 return ret;
0200
0201 clocksource_register_hz(&suspend_clocksource,
0202 timer_of_rate(&suspend_to));
0203
0204 return 0;
0205 }
0206
0207 TIMER_OF_DECLARE(sc9860_timer, "sprd,sc9860-timer", sprd_timer_init);
0208 TIMER_OF_DECLARE(sc9860_persistent_timer, "sprd,sc9860-suspend-timer",
0209 sprd_suspend_timer_init);
