drivers/clocksource/timer-sp804.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  linux/drivers/clocksource/timer-sp.c
0004  *
0005  *  Copyright (C) 1999 - 2003 ARM Limited
0006  *  Copyright (C) 2000 Deep Blue Solutions Ltd
0007  */
0008
0009 #define pr_fmt(fmt)    KBUILD_MODNAME ": " fmt
0010
0011 #include <linux/clk.h>
0012 #include <linux/clocksource.h>
0013 #include <linux/clockchips.h>
0014 #include <linux/err.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/irq.h>
0017 #include <linux/io.h>
0018 #include <linux/of.h>
0019 #include <linux/of_address.h>
0020 #include <linux/of_clk.h>
0021 #include <linux/of_irq.h>
0022 #include <linux/sched_clock.h>
0023
0024 #include "timer-sp.h"
0025
0026 /* Hisilicon 64-bit timer(a variant of ARM SP804) */
0027 #define HISI_TIMER_1_BASE   0x00
0028 #define HISI_TIMER_2_BASE   0x40
0029 #define HISI_TIMER_LOAD     0x00
0030 #define HISI_TIMER_LOAD_H   0x04
0031 #define HISI_TIMER_VALUE    0x08
0032 #define HISI_TIMER_VALUE_H  0x0c
0033 #define HISI_TIMER_CTRL     0x10
0034 #define HISI_TIMER_INTCLR   0x14
0035 #define HISI_TIMER_RIS      0x18
0036 #define HISI_TIMER_MIS      0x1c
0037 #define HISI_TIMER_BGLOAD   0x20
0038 #define HISI_TIMER_BGLOAD_H 0x24
0039
0040 static struct sp804_timer arm_sp804_timer __initdata = {
0041     .load       = TIMER_LOAD,
0042     .value      = TIMER_VALUE,
0043     .ctrl       = TIMER_CTRL,
0044     .intclr     = TIMER_INTCLR,
0045     .timer_base = {TIMER_1_BASE, TIMER_2_BASE},
0046     .width      = 32,
0047 };
0048
0049 static struct sp804_timer hisi_sp804_timer __initdata = {
0050     .load       = HISI_TIMER_LOAD,
0051     .load_h     = HISI_TIMER_LOAD_H,
0052     .value      = HISI_TIMER_VALUE,
0053     .value_h    = HISI_TIMER_VALUE_H,
0054     .ctrl       = HISI_TIMER_CTRL,
0055     .intclr     = HISI_TIMER_INTCLR,
0056     .timer_base = {HISI_TIMER_1_BASE, HISI_TIMER_2_BASE},
0057     .width      = 64,
0058 };
0059
0060 static struct sp804_clkevt sp804_clkevt[NR_TIMERS];
0061
0062 static long __init sp804_get_clock_rate(struct clk *clk, const char *name)
0063 {
0064     int err;
0065
0066     if (!clk)
0067         clk = clk_get_sys("sp804", name);
0068     if (IS_ERR(clk)) {
0069         pr_err("%s clock not found: %ld\n", name, PTR_ERR(clk));
0070         return PTR_ERR(clk);
0071     }
0072
0073     err = clk_prepare_enable(clk);
0074     if (err) {
0075         pr_err("clock failed to enable: %d\n", err);
0076         clk_put(clk);
0077         return err;
0078     }
0079
0080     return clk_get_rate(clk);
0081 }
0082
0083 static struct sp804_clkevt * __init sp804_clkevt_get(void __iomem *base)
0084 {
0085     int i;
0086
0087     for (i = 0; i < NR_TIMERS; i++) {
0088         if (sp804_clkevt[i].base == base)
0089             return &sp804_clkevt[i];
0090     }
0091
0092     /* It's impossible to reach here */
0093     WARN_ON(1);
0094
0095     return NULL;
0096 }
0097
0098 static struct sp804_clkevt *sched_clkevt;
0099
0100 static u64 notrace sp804_read(void)
0101 {
0102     return ~readl_relaxed(sched_clkevt->value);
0103 }
0104
0105 static int __init sp804_clocksource_and_sched_clock_init(void __iomem *base,
0106                              const char *name,
0107                              struct clk *clk,
0108                              int use_sched_clock)
0109 {
0110     long rate;
0111     struct sp804_clkevt *clkevt;
0112
0113     rate = sp804_get_clock_rate(clk, name);
0114     if (rate < 0)
0115         return -EINVAL;
0116
0117     clkevt = sp804_clkevt_get(base);
0118
0119     writel(0, clkevt->ctrl);
0120     writel(0xffffffff, clkevt->load);
0121     writel(0xffffffff, clkevt->value);
0122     if (clkevt->width == 64) {
0123         writel(0xffffffff, clkevt->load_h);
0124         writel(0xffffffff, clkevt->value_h);
0125     }
0126     writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
0127         clkevt->ctrl);
0128
0129     clocksource_mmio_init(clkevt->value, name,
0130         rate, 200, 32, clocksource_mmio_readl_down);
0131
0132     if (use_sched_clock) {
0133         sched_clkevt = clkevt;
0134         sched_clock_register(sp804_read, 32, rate);
0135     }
0136
0137     return 0;
0138 }
0139
0140
0141 static struct sp804_clkevt *common_clkevt;
0142
0143 /*
0144  * IRQ handler for the timer
0145  */
0146 static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
0147 {
0148     struct clock_event_device *evt = dev_id;
0149
0150     /* clear the interrupt */
0151     writel(1, common_clkevt->intclr);
0152
0153     evt->event_handler(evt);
0154
0155     return IRQ_HANDLED;
0156 }
0157
0158 static inline void timer_shutdown(struct clock_event_device *evt)
0159 {
0160     writel(0, common_clkevt->ctrl);
0161 }
0162
0163 static int sp804_shutdown(struct clock_event_device *evt)
0164 {
0165     timer_shutdown(evt);
0166     return 0;
0167 }
0168
0169 static int sp804_set_periodic(struct clock_event_device *evt)
0170 {
0171     unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
0172                  TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
0173
0174     timer_shutdown(evt);
0175     writel(common_clkevt->reload, common_clkevt->load);
0176     writel(ctrl, common_clkevt->ctrl);
0177     return 0;
0178 }
0179
0180 static int sp804_set_next_event(unsigned long next,
0181     struct clock_event_device *evt)
0182 {
0183     unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
0184                  TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE;
0185
0186     writel(next, common_clkevt->load);
0187     writel(ctrl, common_clkevt->ctrl);
0188
0189     return 0;
0190 }
0191
0192 static struct clock_event_device sp804_clockevent = {
0193     .features       = CLOCK_EVT_FEAT_PERIODIC |
0194                   CLOCK_EVT_FEAT_ONESHOT |
0195                   CLOCK_EVT_FEAT_DYNIRQ,
0196     .set_state_shutdown = sp804_shutdown,
0197     .set_state_periodic = sp804_set_periodic,
0198     .set_state_oneshot  = sp804_shutdown,
0199     .tick_resume        = sp804_shutdown,
0200     .set_next_event     = sp804_set_next_event,
0201     .rating         = 300,
0202 };
0203
0204 static int __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
0205                      struct clk *clk, const char *name)
0206 {
0207     struct clock_event_device *evt = &sp804_clockevent;
0208     long rate;
0209
0210     rate = sp804_get_clock_rate(clk, name);
0211     if (rate < 0)
0212         return -EINVAL;
0213
0214     common_clkevt = sp804_clkevt_get(base);
0215     common_clkevt->reload = DIV_ROUND_CLOSEST(rate, HZ);
0216     evt->name = name;
0217     evt->irq = irq;
0218     evt->cpumask = cpu_possible_mask;
0219
0220     writel(0, common_clkevt->ctrl);
0221
0222     if (request_irq(irq, sp804_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
0223             "timer", &sp804_clockevent))
0224         pr_err("request_irq() failed\n");
0225     clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
0226
0227     return 0;
0228 }
0229
0230 static void __init sp804_clkevt_init(struct sp804_timer *timer, void __iomem *base)
0231 {
0232     int i;
0233
0234     for (i = 0; i < NR_TIMERS; i++) {
0235         void __iomem *timer_base;
0236         struct sp804_clkevt *clkevt;
0237
0238         timer_base = base + timer->timer_base[i];
0239         clkevt = &sp804_clkevt[i];
0240         clkevt->base    = timer_base;
0241         clkevt->load    = timer_base + timer->load;
0242         clkevt->load_h  = timer_base + timer->load_h;
0243         clkevt->value   = timer_base + timer->value;
0244         clkevt->value_h = timer_base + timer->value_h;
0245         clkevt->ctrl    = timer_base + timer->ctrl;
0246         clkevt->intclr  = timer_base + timer->intclr;
0247         clkevt->width   = timer->width;
0248     }
0249 }
0250
0251 static int __init sp804_of_init(struct device_node *np, struct sp804_timer *timer)
0252 {
0253     static bool initialized = false;
0254     void __iomem *base;
0255     void __iomem *timer1_base;
0256     void __iomem *timer2_base;
0257     int irq, ret = -EINVAL;
0258     u32 irq_num = 0;
0259     struct clk *clk1, *clk2;
0260     const char *name = of_get_property(np, "compatible", NULL);
0261
0262     if (initialized) {
0263         pr_debug("%pOF: skipping further SP804 timer device\n", np);
0264         return 0;
0265     }
0266
0267     base = of_iomap(np, 0);
0268     if (!base)
0269         return -ENXIO;
0270
0271     timer1_base = base + timer->timer_base[0];
0272     timer2_base = base + timer->timer_base[1];
0273
0274     /* Ensure timers are disabled */
0275     writel(0, timer1_base + timer->ctrl);
0276     writel(0, timer2_base + timer->ctrl);
0277
0278     clk1 = of_clk_get(np, 0);
0279     if (IS_ERR(clk1))
0280         clk1 = NULL;
0281
0282     /* Get the 2nd clock if the timer has 3 timer clocks */
0283     if (of_clk_get_parent_count(np) == 3) {
0284         clk2 = of_clk_get(np, 1);
0285         if (IS_ERR(clk2)) {
0286             pr_err("%pOFn clock not found: %d\n", np,
0287                 (int)PTR_ERR(clk2));
0288             clk2 = NULL;
0289         }
0290     } else
0291         clk2 = clk1;
0292
0293     irq = irq_of_parse_and_map(np, 0);
0294     if (irq <= 0)
0295         goto err;
0296
0297     sp804_clkevt_init(timer, base);
0298
0299     of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
0300     if (irq_num == 2) {
0301
0302         ret = sp804_clockevents_init(timer2_base, irq, clk2, name);
0303         if (ret)
0304             goto err;
0305
0306         ret = sp804_clocksource_and_sched_clock_init(timer1_base,
0307                                  name, clk1, 1);
0308         if (ret)
0309             goto err;
0310     } else {
0311
0312         ret = sp804_clockevents_init(timer1_base, irq, clk1, name);
0313         if (ret)
0314             goto err;
0315
0316         ret = sp804_clocksource_and_sched_clock_init(timer2_base,
0317                                  name, clk2, 1);
0318         if (ret)
0319             goto err;
0320     }
0321     initialized = true;
0322
0323     return 0;
0324 err:
0325     iounmap(base);
0326     return ret;
0327 }
0328
0329 static int __init arm_sp804_of_init(struct device_node *np)
0330 {
0331     return sp804_of_init(np, &arm_sp804_timer);
0332 }
0333 TIMER_OF_DECLARE(sp804, "arm,sp804", arm_sp804_of_init);
0334
0335 static int __init hisi_sp804_of_init(struct device_node *np)
0336 {
0337     return sp804_of_init(np, &hisi_sp804_timer);
0338 }
0339 TIMER_OF_DECLARE(hisi_sp804, "hisilicon,sp804", hisi_sp804_of_init);
0340
0341 static int __init integrator_cp_of_init(struct device_node *np)
0342 {
0343     static int init_count = 0;
0344     void __iomem *base;
0345     int irq, ret = -EINVAL;
0346     const char *name = of_get_property(np, "compatible", NULL);
0347     struct clk *clk;
0348
0349     base = of_iomap(np, 0);
0350     if (!base) {
0351         pr_err("Failed to iomap\n");
0352         return -ENXIO;
0353     }
0354
0355     clk = of_clk_get(np, 0);
0356     if (IS_ERR(clk)) {
0357         pr_err("Failed to get clock\n");
0358         return PTR_ERR(clk);
0359     }
0360
0361     /* Ensure timer is disabled */
0362     writel(0, base + arm_sp804_timer.ctrl);
0363
0364     if (init_count == 2 || !of_device_is_available(np))
0365         goto err;
0366
0367     sp804_clkevt_init(&arm_sp804_timer, base);
0368
0369     if (!init_count) {
0370         ret = sp804_clocksource_and_sched_clock_init(base,
0371                                  name, clk, 0);
0372         if (ret)
0373             goto err;
0374     } else {
0375         irq = irq_of_parse_and_map(np, 0);
0376         if (irq <= 0)
0377             goto err;
0378
0379         ret = sp804_clockevents_init(base, irq, clk, name);
0380         if (ret)
0381             goto err;
0382     }
0383
0384     init_count++;
0385     return 0;
0386 err:
0387     iounmap(base);
0388     return ret;
0389 }
0390 TIMER_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);