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0013 #define NR_TIMERS 2
0014 #define TIMER_1_BASE 0x00
0015 #define TIMER_2_BASE 0x20
0016
0017 #define TIMER_LOAD 0x00
0018 #define TIMER_VALUE 0x04
0019 #define TIMER_CTRL 0x08
0020 #define TIMER_CTRL_ONESHOT (1 << 0)
0021 #define TIMER_CTRL_32BIT (1 << 1)
0022 #define TIMER_CTRL_DIV1 (0 << 2)
0023 #define TIMER_CTRL_DIV16 (1 << 2)
0024 #define TIMER_CTRL_DIV256 (2 << 2)
0025 #define TIMER_CTRL_IE (1 << 5)
0026 #define TIMER_CTRL_PERIODIC (1 << 6)
0027 #define TIMER_CTRL_ENABLE (1 << 7)
0028
0029 #define TIMER_INTCLR 0x0c
0030 #define TIMER_RIS 0x10
0031 #define TIMER_MIS 0x14
0032 #define TIMER_BGLOAD 0x18
0033
0034 struct sp804_timer {
0035 int load;
0036 int load_h;
0037 int value;
0038 int value_h;
0039 int ctrl;
0040 int intclr;
0041 int ris;
0042 int mis;
0043 int bgload;
0044 int bgload_h;
0045 int timer_base[NR_TIMERS];
0046 int width;
0047 };
0048
0049 struct sp804_clkevt {
0050 void __iomem *base;
0051 void __iomem *load;
0052 void __iomem *load_h;
0053 void __iomem *value;
0054 void __iomem *value_h;
0055 void __iomem *ctrl;
0056 void __iomem *intclr;
0057 void __iomem *ris;
0058 void __iomem *mis;
0059 void __iomem *bgload;
0060 void __iomem *bgload_h;
0061 unsigned long reload;
0062 int width;
0063 };