drivers/clocksource/timer-rockchip.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Rockchip timer support
0004  *
0005  * Copyright (C) Daniel Lezcano <daniel.lezcano@linaro.org>
0006  */
0007 #include <linux/clk.h>
0008 #include <linux/clockchips.h>
0009 #include <linux/init.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/sched_clock.h>
0012 #include <linux/slab.h>
0013 #include <linux/of.h>
0014 #include <linux/of_address.h>
0015 #include <linux/of_irq.h>
0016
0017 #define TIMER_NAME "rk_timer"
0018
0019 #define TIMER_LOAD_COUNT0   0x00
0020 #define TIMER_LOAD_COUNT1   0x04
0021 #define TIMER_CURRENT_VALUE0    0x08
0022 #define TIMER_CURRENT_VALUE1    0x0C
0023 #define TIMER_CONTROL_REG3288   0x10
0024 #define TIMER_CONTROL_REG3399   0x1c
0025 #define TIMER_INT_STATUS    0x18
0026
0027 #define TIMER_DISABLE       0x0
0028 #define TIMER_ENABLE        0x1
0029 #define TIMER_MODE_FREE_RUNNING         (0 << 1)
0030 #define TIMER_MODE_USER_DEFINED_COUNT       (1 << 1)
0031 #define TIMER_INT_UNMASK            (1 << 2)
0032
0033 struct rk_timer {
0034     void __iomem *base;
0035     void __iomem *ctrl;
0036     struct clk *clk;
0037     struct clk *pclk;
0038     u32 freq;
0039     int irq;
0040 };
0041
0042 struct rk_clkevt {
0043     struct clock_event_device ce;
0044     struct rk_timer timer;
0045 };
0046
0047 static struct rk_clkevt *rk_clkevt;
0048 static struct rk_timer *rk_clksrc;
0049
0050 static inline struct rk_timer *rk_timer(struct clock_event_device *ce)
0051 {
0052     return &container_of(ce, struct rk_clkevt, ce)->timer;
0053 }
0054
0055 static inline void rk_timer_disable(struct rk_timer *timer)
0056 {
0057     writel_relaxed(TIMER_DISABLE, timer->ctrl);
0058 }
0059
0060 static inline void rk_timer_enable(struct rk_timer *timer, u32 flags)
0061 {
0062     writel_relaxed(TIMER_ENABLE | flags, timer->ctrl);
0063 }
0064
0065 static void rk_timer_update_counter(unsigned long cycles,
0066                     struct rk_timer *timer)
0067 {
0068     writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0);
0069     writel_relaxed(0, timer->base + TIMER_LOAD_COUNT1);
0070 }
0071
0072 static void rk_timer_interrupt_clear(struct rk_timer *timer)
0073 {
0074     writel_relaxed(1, timer->base + TIMER_INT_STATUS);
0075 }
0076
0077 static inline int rk_timer_set_next_event(unsigned long cycles,
0078                       struct clock_event_device *ce)
0079 {
0080     struct rk_timer *timer = rk_timer(ce);
0081
0082     rk_timer_disable(timer);
0083     rk_timer_update_counter(cycles, timer);
0084     rk_timer_enable(timer, TIMER_MODE_USER_DEFINED_COUNT |
0085                    TIMER_INT_UNMASK);
0086     return 0;
0087 }
0088
0089 static int rk_timer_shutdown(struct clock_event_device *ce)
0090 {
0091     struct rk_timer *timer = rk_timer(ce);
0092
0093     rk_timer_disable(timer);
0094     return 0;
0095 }
0096
0097 static int rk_timer_set_periodic(struct clock_event_device *ce)
0098 {
0099     struct rk_timer *timer = rk_timer(ce);
0100
0101     rk_timer_disable(timer);
0102     rk_timer_update_counter(timer->freq / HZ - 1, timer);
0103     rk_timer_enable(timer, TIMER_MODE_FREE_RUNNING | TIMER_INT_UNMASK);
0104     return 0;
0105 }
0106
0107 static irqreturn_t rk_timer_interrupt(int irq, void *dev_id)
0108 {
0109     struct clock_event_device *ce = dev_id;
0110     struct rk_timer *timer = rk_timer(ce);
0111
0112     rk_timer_interrupt_clear(timer);
0113
0114     if (clockevent_state_oneshot(ce))
0115         rk_timer_disable(timer);
0116
0117     ce->event_handler(ce);
0118
0119     return IRQ_HANDLED;
0120 }
0121
0122 static u64 notrace rk_timer_sched_read(void)
0123 {
0124     return ~readl_relaxed(rk_clksrc->base + TIMER_CURRENT_VALUE0);
0125 }
0126
0127 static int __init
0128 rk_timer_probe(struct rk_timer *timer, struct device_node *np)
0129 {
0130     struct clk *timer_clk;
0131     struct clk *pclk;
0132     int ret = -EINVAL, irq;
0133     u32 ctrl_reg = TIMER_CONTROL_REG3288;
0134
0135     timer->base = of_iomap(np, 0);
0136     if (!timer->base) {
0137         pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
0138         return -ENXIO;
0139     }
0140
0141     if (of_device_is_compatible(np, "rockchip,rk3399-timer"))
0142         ctrl_reg = TIMER_CONTROL_REG3399;
0143
0144     timer->ctrl = timer->base + ctrl_reg;
0145
0146     pclk = of_clk_get_by_name(np, "pclk");
0147     if (IS_ERR(pclk)) {
0148         ret = PTR_ERR(pclk);
0149         pr_err("Failed to get pclk for '%s'\n", TIMER_NAME);
0150         goto out_unmap;
0151     }
0152
0153     ret = clk_prepare_enable(pclk);
0154     if (ret) {
0155         pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
0156         goto out_unmap;
0157     }
0158     timer->pclk = pclk;
0159
0160     timer_clk = of_clk_get_by_name(np, "timer");
0161     if (IS_ERR(timer_clk)) {
0162         ret = PTR_ERR(timer_clk);
0163         pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME);
0164         goto out_timer_clk;
0165     }
0166
0167     ret = clk_prepare_enable(timer_clk);
0168     if (ret) {
0169         pr_err("Failed to enable timer clock\n");
0170         goto out_timer_clk;
0171     }
0172     timer->clk = timer_clk;
0173
0174     timer->freq = clk_get_rate(timer_clk);
0175
0176     irq = irq_of_parse_and_map(np, 0);
0177     if (!irq) {
0178         ret = -EINVAL;
0179         pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME);
0180         goto out_irq;
0181     }
0182     timer->irq = irq;
0183
0184     rk_timer_interrupt_clear(timer);
0185     rk_timer_disable(timer);
0186     return 0;
0187
0188 out_irq:
0189     clk_disable_unprepare(timer_clk);
0190 out_timer_clk:
0191     clk_disable_unprepare(pclk);
0192 out_unmap:
0193     iounmap(timer->base);
0194
0195     return ret;
0196 }
0197
0198 static void __init rk_timer_cleanup(struct rk_timer *timer)
0199 {
0200     clk_disable_unprepare(timer->clk);
0201     clk_disable_unprepare(timer->pclk);
0202     iounmap(timer->base);
0203 }
0204
0205 static int __init rk_clkevt_init(struct device_node *np)
0206 {
0207     struct clock_event_device *ce;
0208     int ret = -EINVAL;
0209
0210     rk_clkevt = kzalloc(sizeof(struct rk_clkevt), GFP_KERNEL);
0211     if (!rk_clkevt) {
0212         ret = -ENOMEM;
0213         goto out;
0214     }
0215
0216     ret = rk_timer_probe(&rk_clkevt->timer, np);
0217     if (ret)
0218         goto out_probe;
0219
0220     ce = &rk_clkevt->ce;
0221     ce->name = TIMER_NAME;
0222     ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
0223                CLOCK_EVT_FEAT_DYNIRQ;
0224     ce->set_next_event = rk_timer_set_next_event;
0225     ce->set_state_shutdown = rk_timer_shutdown;
0226     ce->set_state_periodic = rk_timer_set_periodic;
0227     ce->irq = rk_clkevt->timer.irq;
0228     ce->cpumask = cpu_possible_mask;
0229     ce->rating = 250;
0230
0231     ret = request_irq(rk_clkevt->timer.irq, rk_timer_interrupt, IRQF_TIMER,
0232               TIMER_NAME, ce);
0233     if (ret) {
0234         pr_err("Failed to initialize '%s': %d\n",
0235             TIMER_NAME, ret);
0236         goto out_irq;
0237     }
0238
0239     clockevents_config_and_register(&rk_clkevt->ce,
0240                     rk_clkevt->timer.freq, 1, UINT_MAX);
0241     return 0;
0242
0243 out_irq:
0244     rk_timer_cleanup(&rk_clkevt->timer);
0245 out_probe:
0246     kfree(rk_clkevt);
0247 out:
0248     /* Leave rk_clkevt not NULL to prevent future init */
0249     rk_clkevt = ERR_PTR(ret);
0250     return ret;
0251 }
0252
0253 static int __init rk_clksrc_init(struct device_node *np)
0254 {
0255     int ret = -EINVAL;
0256
0257     rk_clksrc = kzalloc(sizeof(struct rk_timer), GFP_KERNEL);
0258     if (!rk_clksrc) {
0259         ret = -ENOMEM;
0260         goto out;
0261     }
0262
0263     ret = rk_timer_probe(rk_clksrc, np);
0264     if (ret)
0265         goto out_probe;
0266
0267     rk_timer_update_counter(UINT_MAX, rk_clksrc);
0268     rk_timer_enable(rk_clksrc, 0);
0269
0270     ret = clocksource_mmio_init(rk_clksrc->base + TIMER_CURRENT_VALUE0,
0271         TIMER_NAME, rk_clksrc->freq, 250, 32,
0272         clocksource_mmio_readl_down);
0273     if (ret) {
0274         pr_err("Failed to register clocksource\n");
0275         goto out_clocksource;
0276     }
0277
0278     sched_clock_register(rk_timer_sched_read, 32, rk_clksrc->freq);
0279     return 0;
0280
0281 out_clocksource:
0282     rk_timer_cleanup(rk_clksrc);
0283 out_probe:
0284     kfree(rk_clksrc);
0285 out:
0286     /* Leave rk_clksrc not NULL to prevent future init */
0287     rk_clksrc = ERR_PTR(ret);
0288     return ret;
0289 }
0290
0291 static int __init rk_timer_init(struct device_node *np)
0292 {
0293     if (!rk_clkevt)
0294         return rk_clkevt_init(np);
0295
0296     if (!rk_clksrc)
0297         return rk_clksrc_init(np);
0298
0299     pr_err("Too many timer definitions for '%s'\n", TIMER_NAME);
0300     return -EINVAL;
0301 }
0302
0303 TIMER_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", rk_timer_init);
0304 TIMER_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", rk_timer_init);