drivers/clocksource/timer-riscv.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2012 Regents of the University of California
0004  * Copyright (C) 2017 SiFive
0005  *
0006  * All RISC-V systems have a timer attached to every hart.  These timers can
0007  * either be read from the "time" and "timeh" CSRs, and can use the SBI to
0008  * setup events, or directly accessed using MMIO registers.
0009  */
0010
0011 #define pr_fmt(fmt) "riscv-timer: " fmt
0012
0013 #include <linux/clocksource.h>
0014 #include <linux/clockchips.h>
0015 #include <linux/cpu.h>
0016 #include <linux/delay.h>
0017 #include <linux/irq.h>
0018 #include <linux/irqdomain.h>
0019 #include <linux/module.h>
0020 #include <linux/sched_clock.h>
0021 #include <linux/io-64-nonatomic-lo-hi.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/of_irq.h>
0024 #include <clocksource/timer-riscv.h>
0025 #include <asm/smp.h>
0026 #include <asm/hwcap.h>
0027 #include <asm/sbi.h>
0028 #include <asm/timex.h>
0029
0030 static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
0031
0032 static int riscv_clock_next_event(unsigned long delta,
0033         struct clock_event_device *ce)
0034 {
0035     u64 next_tval = get_cycles64() + delta;
0036
0037     csr_set(CSR_IE, IE_TIE);
0038     if (static_branch_likely(&riscv_sstc_available)) {
0039 #if defined(CONFIG_32BIT)
0040         csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF);
0041         csr_write(CSR_STIMECMPH, next_tval >> 32);
0042 #else
0043         csr_write(CSR_STIMECMP, next_tval);
0044 #endif
0045     } else
0046         sbi_set_timer(next_tval);
0047
0048     return 0;
0049 }
0050
0051 static unsigned int riscv_clock_event_irq;
0052 static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
0053     .name           = "riscv_timer_clockevent",
0054     .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP,
0055     .rating         = 100,
0056     .set_next_event     = riscv_clock_next_event,
0057 };
0058
0059 /*
0060  * It is guaranteed that all the timers across all the harts are synchronized
0061  * within one tick of each other, so while this could technically go
0062  * backwards when hopping between CPUs, practically it won't happen.
0063  */
0064 static unsigned long long riscv_clocksource_rdtime(struct clocksource *cs)
0065 {
0066     return get_cycles64();
0067 }
0068
0069 static u64 notrace riscv_sched_clock(void)
0070 {
0071     return get_cycles64();
0072 }
0073
0074 static struct clocksource riscv_clocksource = {
0075     .name       = "riscv_clocksource",
0076     .rating     = 300,
0077     .mask       = CLOCKSOURCE_MASK(64),
0078     .flags      = CLOCK_SOURCE_IS_CONTINUOUS,
0079     .read       = riscv_clocksource_rdtime,
0080 };
0081
0082 static int riscv_timer_starting_cpu(unsigned int cpu)
0083 {
0084     struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu);
0085
0086     ce->cpumask = cpumask_of(cpu);
0087     ce->irq = riscv_clock_event_irq;
0088     clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
0089
0090     enable_percpu_irq(riscv_clock_event_irq,
0091               irq_get_trigger_type(riscv_clock_event_irq));
0092     return 0;
0093 }
0094
0095 static int riscv_timer_dying_cpu(unsigned int cpu)
0096 {
0097     disable_percpu_irq(riscv_clock_event_irq);
0098     return 0;
0099 }
0100
0101 void riscv_cs_get_mult_shift(u32 *mult, u32 *shift)
0102 {
0103     *mult = riscv_clocksource.mult;
0104     *shift = riscv_clocksource.shift;
0105 }
0106 EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift);
0107
0108 /* called directly from the low-level interrupt handler */
0109 static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
0110 {
0111     struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
0112
0113     csr_clear(CSR_IE, IE_TIE);
0114     evdev->event_handler(evdev);
0115
0116     return IRQ_HANDLED;
0117 }
0118
0119 static int __init riscv_timer_init_dt(struct device_node *n)
0120 {
0121     int cpuid, error;
0122     unsigned long hartid;
0123     struct device_node *child;
0124     struct irq_domain *domain;
0125
0126     error = riscv_of_processor_hartid(n, &hartid);
0127     if (error < 0) {
0128         pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n",
0129             n, hartid);
0130         return error;
0131     }
0132
0133     cpuid = riscv_hartid_to_cpuid(hartid);
0134     if (cpuid < 0) {
0135         pr_warn("Invalid cpuid for hartid [%lu]\n", hartid);
0136         return cpuid;
0137     }
0138
0139     if (cpuid != smp_processor_id())
0140         return 0;
0141
0142     domain = NULL;
0143     child = of_get_compatible_child(n, "riscv,cpu-intc");
0144     if (!child) {
0145         pr_err("Failed to find INTC node [%pOF]\n", n);
0146         return -ENODEV;
0147     }
0148     domain = irq_find_host(child);
0149     of_node_put(child);
0150     if (!domain) {
0151         pr_err("Failed to find IRQ domain for node [%pOF]\n", n);
0152         return -ENODEV;
0153     }
0154
0155     riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER);
0156     if (!riscv_clock_event_irq) {
0157         pr_err("Failed to map timer interrupt for node [%pOF]\n", n);
0158         return -ENODEV;
0159     }
0160
0161     pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n",
0162            __func__, cpuid, hartid);
0163     error = clocksource_register_hz(&riscv_clocksource, riscv_timebase);
0164     if (error) {
0165         pr_err("RISCV timer register failed [%d] for cpu = [%d]\n",
0166                error, cpuid);
0167         return error;
0168     }
0169
0170     sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
0171
0172     error = request_percpu_irq(riscv_clock_event_irq,
0173                     riscv_timer_interrupt,
0174                     "riscv-timer", &riscv_clock_event);
0175     if (error) {
0176         pr_err("registering percpu irq failed [%d]\n", error);
0177         return error;
0178     }
0179
0180     error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
0181              "clockevents/riscv/timer:starting",
0182              riscv_timer_starting_cpu, riscv_timer_dying_cpu);
0183     if (error)
0184         pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
0185                error);
0186
0187     if (riscv_isa_extension_available(NULL, SSTC)) {
0188         pr_info("Timer interrupt in S-mode is available via sstc extension\n");
0189         static_branch_enable(&riscv_sstc_available);
0190     }
0191
0192     return error;
0193 }
0194
0195 TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt);