drivers/clocksource/timer-qcom.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  * Copyright (C) 2007 Google, Inc.
0005  * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
0006  */
0007
0008 #include <linux/clocksource.h>
0009 #include <linux/clockchips.h>
0010 #include <linux/cpu.h>
0011 #include <linux/init.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/irq.h>
0014 #include <linux/io.h>
0015 #include <linux/of.h>
0016 #include <linux/of_address.h>
0017 #include <linux/of_irq.h>
0018 #include <linux/sched_clock.h>
0019
0020 #include <asm/delay.h>
0021
0022 #define TIMER_MATCH_VAL         0x0000
0023 #define TIMER_COUNT_VAL         0x0004
0024 #define TIMER_ENABLE            0x0008
0025 #define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
0026 #define TIMER_ENABLE_EN         BIT(0)
0027 #define TIMER_CLEAR         0x000C
0028 #define DGT_CLK_CTL         0x10
0029 #define DGT_CLK_CTL_DIV_4       0x3
0030 #define TIMER_STS_GPT0_CLR_PEND     BIT(10)
0031
0032 #define GPT_HZ 32768
0033
0034 static void __iomem *event_base;
0035 static void __iomem *sts_base;
0036
0037 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
0038 {
0039     struct clock_event_device *evt = dev_id;
0040     /* Stop the timer tick */
0041     if (clockevent_state_oneshot(evt)) {
0042         u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
0043         ctrl &= ~TIMER_ENABLE_EN;
0044         writel_relaxed(ctrl, event_base + TIMER_ENABLE);
0045     }
0046     evt->event_handler(evt);
0047     return IRQ_HANDLED;
0048 }
0049
0050 static int msm_timer_set_next_event(unsigned long cycles,
0051                     struct clock_event_device *evt)
0052 {
0053     u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
0054
0055     ctrl &= ~TIMER_ENABLE_EN;
0056     writel_relaxed(ctrl, event_base + TIMER_ENABLE);
0057
0058     writel_relaxed(ctrl, event_base + TIMER_CLEAR);
0059     writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
0060
0061     if (sts_base)
0062         while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
0063             cpu_relax();
0064
0065     writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
0066     return 0;
0067 }
0068
0069 static int msm_timer_shutdown(struct clock_event_device *evt)
0070 {
0071     u32 ctrl;
0072
0073     ctrl = readl_relaxed(event_base + TIMER_ENABLE);
0074     ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
0075     writel_relaxed(ctrl, event_base + TIMER_ENABLE);
0076     return 0;
0077 }
0078
0079 static struct clock_event_device __percpu *msm_evt;
0080
0081 static void __iomem *source_base;
0082
0083 static notrace u64 msm_read_timer_count(struct clocksource *cs)
0084 {
0085     return readl_relaxed(source_base + TIMER_COUNT_VAL);
0086 }
0087
0088 static struct clocksource msm_clocksource = {
0089     .name   = "dg_timer",
0090     .rating = 300,
0091     .read   = msm_read_timer_count,
0092     .mask   = CLOCKSOURCE_MASK(32),
0093     .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
0094 };
0095
0096 static int msm_timer_irq;
0097 static int msm_timer_has_ppi;
0098
0099 static int msm_local_timer_starting_cpu(unsigned int cpu)
0100 {
0101     struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu);
0102     int err;
0103
0104     evt->irq = msm_timer_irq;
0105     evt->name = "msm_timer";
0106     evt->features = CLOCK_EVT_FEAT_ONESHOT;
0107     evt->rating = 200;
0108     evt->set_state_shutdown = msm_timer_shutdown;
0109     evt->set_state_oneshot = msm_timer_shutdown;
0110     evt->tick_resume = msm_timer_shutdown;
0111     evt->set_next_event = msm_timer_set_next_event;
0112     evt->cpumask = cpumask_of(cpu);
0113
0114     clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
0115
0116     if (msm_timer_has_ppi) {
0117         enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
0118     } else {
0119         err = request_irq(evt->irq, msm_timer_interrupt,
0120                 IRQF_TIMER | IRQF_NOBALANCING |
0121                 IRQF_TRIGGER_RISING, "gp_timer", evt);
0122         if (err)
0123             pr_err("request_irq failed\n");
0124     }
0125
0126     return 0;
0127 }
0128
0129 static int msm_local_timer_dying_cpu(unsigned int cpu)
0130 {
0131     struct clock_event_device *evt = per_cpu_ptr(msm_evt, cpu);
0132
0133     evt->set_state_shutdown(evt);
0134     disable_percpu_irq(evt->irq);
0135     return 0;
0136 }
0137
0138 static u64 notrace msm_sched_clock_read(void)
0139 {
0140     return msm_clocksource.read(&msm_clocksource);
0141 }
0142
0143 static unsigned long msm_read_current_timer(void)
0144 {
0145     return msm_clocksource.read(&msm_clocksource);
0146 }
0147
0148 static struct delay_timer msm_delay_timer = {
0149     .read_current_timer = msm_read_current_timer,
0150 };
0151
0152 static int __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
0153                   bool percpu)
0154 {
0155     struct clocksource *cs = &msm_clocksource;
0156     int res = 0;
0157
0158     msm_timer_irq = irq;
0159     msm_timer_has_ppi = percpu;
0160
0161     msm_evt = alloc_percpu(struct clock_event_device);
0162     if (!msm_evt) {
0163         pr_err("memory allocation failed for clockevents\n");
0164         goto err;
0165     }
0166
0167     if (percpu)
0168         res = request_percpu_irq(irq, msm_timer_interrupt,
0169                      "gp_timer", msm_evt);
0170
0171     if (res) {
0172         pr_err("request_percpu_irq failed\n");
0173     } else {
0174         /* Install and invoke hotplug callbacks */
0175         res = cpuhp_setup_state(CPUHP_AP_QCOM_TIMER_STARTING,
0176                     "clockevents/qcom/timer:starting",
0177                     msm_local_timer_starting_cpu,
0178                     msm_local_timer_dying_cpu);
0179         if (res) {
0180             free_percpu_irq(irq, msm_evt);
0181             goto err;
0182         }
0183     }
0184
0185 err:
0186     writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
0187     res = clocksource_register_hz(cs, dgt_hz);
0188     if (res)
0189         pr_err("clocksource_register failed\n");
0190     sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
0191     msm_delay_timer.freq = dgt_hz;
0192     register_current_timer_delay(&msm_delay_timer);
0193
0194     return res;
0195 }
0196
0197 static int __init msm_dt_timer_init(struct device_node *np)
0198 {
0199     u32 freq;
0200     int irq, ret;
0201     struct resource res;
0202     u32 percpu_offset;
0203     void __iomem *base;
0204     void __iomem *cpu0_base;
0205
0206     base = of_iomap(np, 0);
0207     if (!base) {
0208         pr_err("Failed to map event base\n");
0209         return -ENXIO;
0210     }
0211
0212     /* We use GPT0 for the clockevent */
0213     irq = irq_of_parse_and_map(np, 1);
0214     if (irq <= 0) {
0215         pr_err("Can't get irq\n");
0216         return -EINVAL;
0217     }
0218
0219     /* We use CPU0's DGT for the clocksource */
0220     if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
0221         percpu_offset = 0;
0222
0223     ret = of_address_to_resource(np, 0, &res);
0224     if (ret) {
0225         pr_err("Failed to parse DGT resource\n");
0226         return ret;
0227     }
0228
0229     cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
0230     if (!cpu0_base) {
0231         pr_err("Failed to map source base\n");
0232         return -EINVAL;
0233     }
0234
0235     if (of_property_read_u32(np, "clock-frequency", &freq)) {
0236         pr_err("Unknown frequency\n");
0237         return -EINVAL;
0238     }
0239
0240     event_base = base + 0x4;
0241     sts_base = base + 0x88;
0242     source_base = cpu0_base + 0x24;
0243     freq /= 4;
0244     writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
0245
0246     return msm_timer_init(freq, 32, irq, !!percpu_offset);
0247 }
0248 TIMER_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
0249 TIMER_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);