drivers/clocksource/timer-pxa.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * arch/arm/mach-pxa/time.c
0004  *
0005  * PXA clocksource, clockevents, and OST interrupt handlers.
0006  * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
0007  *
0008  * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
0009  * by MontaVista Software, Inc.  (Nico, your code rocks!)
0010  */
0011
0012 #include <linux/kernel.h>
0013 #include <linux/init.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/clk.h>
0016 #include <linux/clockchips.h>
0017 #include <linux/of_address.h>
0018 #include <linux/of_irq.h>
0019 #include <linux/sched/clock.h>
0020 #include <linux/sched_clock.h>
0021
0022 #include <clocksource/pxa.h>
0023
0024 #include <asm/div64.h>
0025
0026 #define OSMR0       0x00    /* OS Timer 0 Match Register */
0027 #define OSMR1       0x04    /* OS Timer 1 Match Register */
0028 #define OSMR2       0x08    /* OS Timer 2 Match Register */
0029 #define OSMR3       0x0C    /* OS Timer 3 Match Register */
0030
0031 #define OSCR        0x10    /* OS Timer Counter Register */
0032 #define OSSR        0x14    /* OS Timer Status Register */
0033 #define OWER        0x18    /* OS Timer Watchdog Enable Register */
0034 #define OIER        0x1C    /* OS Timer Interrupt Enable Register */
0035
0036 #define OSSR_M3     (1 << 3)    /* Match status channel 3 */
0037 #define OSSR_M2     (1 << 2)    /* Match status channel 2 */
0038 #define OSSR_M1     (1 << 1)    /* Match status channel 1 */
0039 #define OSSR_M0     (1 << 0)    /* Match status channel 0 */
0040
0041 #define OIER_E0     (1 << 0)    /* Interrupt enable channel 0 */
0042
0043 /*
0044  * This is PXA's sched_clock implementation. This has a resolution
0045  * of at least 308 ns and a maximum value of 208 days.
0046  *
0047  * The return value is guaranteed to be monotonic in that range as
0048  * long as there is always less than 582 seconds between successive
0049  * calls to sched_clock() which should always be the case in practice.
0050  */
0051
0052 #define timer_readl(reg) readl_relaxed(timer_base + (reg))
0053 #define timer_writel(val, reg) writel_relaxed((val), timer_base + (reg))
0054
0055 static void __iomem *timer_base;
0056
0057 static u64 notrace pxa_read_sched_clock(void)
0058 {
0059     return timer_readl(OSCR);
0060 }
0061
0062
0063 #define MIN_OSCR_DELTA 16
0064
0065 static irqreturn_t
0066 pxa_ost0_interrupt(int irq, void *dev_id)
0067 {
0068     struct clock_event_device *c = dev_id;
0069
0070     /* Disarm the compare/match, signal the event. */
0071     timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
0072     timer_writel(OSSR_M0, OSSR);
0073     c->event_handler(c);
0074
0075     return IRQ_HANDLED;
0076 }
0077
0078 static int
0079 pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
0080 {
0081     unsigned long next, oscr;
0082
0083     timer_writel(timer_readl(OIER) | OIER_E0, OIER);
0084     next = timer_readl(OSCR) + delta;
0085     timer_writel(next, OSMR0);
0086     oscr = timer_readl(OSCR);
0087
0088     return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
0089 }
0090
0091 static int pxa_osmr0_shutdown(struct clock_event_device *evt)
0092 {
0093     /* initializing, released, or preparing for suspend */
0094     timer_writel(timer_readl(OIER) & ~OIER_E0, OIER);
0095     timer_writel(OSSR_M0, OSSR);
0096     return 0;
0097 }
0098
0099 #ifdef CONFIG_PM
0100 static unsigned long osmr[4], oier, oscr;
0101
0102 static void pxa_timer_suspend(struct clock_event_device *cedev)
0103 {
0104     osmr[0] = timer_readl(OSMR0);
0105     osmr[1] = timer_readl(OSMR1);
0106     osmr[2] = timer_readl(OSMR2);
0107     osmr[3] = timer_readl(OSMR3);
0108     oier = timer_readl(OIER);
0109     oscr = timer_readl(OSCR);
0110 }
0111
0112 static void pxa_timer_resume(struct clock_event_device *cedev)
0113 {
0114     /*
0115      * Ensure that we have at least MIN_OSCR_DELTA between match
0116      * register 0 and the OSCR, to guarantee that we will receive
0117      * the one-shot timer interrupt.  We adjust OSMR0 in preference
0118      * to OSCR to guarantee that OSCR is monotonically incrementing.
0119      */
0120     if (osmr[0] - oscr < MIN_OSCR_DELTA)
0121         osmr[0] += MIN_OSCR_DELTA;
0122
0123     timer_writel(osmr[0], OSMR0);
0124     timer_writel(osmr[1], OSMR1);
0125     timer_writel(osmr[2], OSMR2);
0126     timer_writel(osmr[3], OSMR3);
0127     timer_writel(oier, OIER);
0128     timer_writel(oscr, OSCR);
0129 }
0130 #else
0131 #define pxa_timer_suspend NULL
0132 #define pxa_timer_resume NULL
0133 #endif
0134
0135 static struct clock_event_device ckevt_pxa_osmr0 = {
0136     .name           = "osmr0",
0137     .features       = CLOCK_EVT_FEAT_ONESHOT,
0138     .rating         = 200,
0139     .set_next_event     = pxa_osmr0_set_next_event,
0140     .set_state_shutdown = pxa_osmr0_shutdown,
0141     .set_state_oneshot  = pxa_osmr0_shutdown,
0142     .suspend        = pxa_timer_suspend,
0143     .resume         = pxa_timer_resume,
0144 };
0145
0146 static int __init pxa_timer_common_init(int irq, unsigned long clock_tick_rate)
0147 {
0148     int ret;
0149
0150     timer_writel(0, OIER);
0151     timer_writel(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
0152
0153     sched_clock_register(pxa_read_sched_clock, 32, clock_tick_rate);
0154
0155     ckevt_pxa_osmr0.cpumask = cpumask_of(0);
0156
0157     ret = request_irq(irq, pxa_ost0_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
0158               "ost0", &ckevt_pxa_osmr0);
0159     if (ret) {
0160         pr_err("Failed to setup irq\n");
0161         return ret;
0162     }
0163
0164     ret = clocksource_mmio_init(timer_base + OSCR, "oscr0", clock_tick_rate, 200,
0165                     32, clocksource_mmio_readl_up);
0166     if (ret) {
0167         pr_err("Failed to init clocksource\n");
0168         return ret;
0169     }
0170
0171     clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate,
0172                     MIN_OSCR_DELTA * 2, 0x7fffffff);
0173
0174     return 0;
0175 }
0176
0177 static int __init pxa_timer_dt_init(struct device_node *np)
0178 {
0179     struct clk *clk;
0180     int irq, ret;
0181
0182     /* timer registers are shared with watchdog timer */
0183     timer_base = of_iomap(np, 0);
0184     if (!timer_base) {
0185         pr_err("%pOFn: unable to map resource\n", np);
0186         return -ENXIO;
0187     }
0188
0189     clk = of_clk_get(np, 0);
0190     if (IS_ERR(clk)) {
0191         pr_crit("%pOFn: unable to get clk\n", np);
0192         return PTR_ERR(clk);
0193     }
0194
0195     ret = clk_prepare_enable(clk);
0196     if (ret) {
0197         pr_crit("Failed to prepare clock\n");
0198         return ret;
0199     }
0200
0201     /* we are only interested in OS-timer0 irq */
0202     irq = irq_of_parse_and_map(np, 0);
0203     if (irq <= 0) {
0204         pr_crit("%pOFn: unable to parse OS-timer0 irq\n", np);
0205         return -EINVAL;
0206     }
0207
0208     return pxa_timer_common_init(irq, clk_get_rate(clk));
0209 }
0210 TIMER_OF_DECLARE(pxa_timer, "marvell,pxa-timer", pxa_timer_dt_init);
0211
0212 /*
0213  * Legacy timer init for non device-tree boards.
0214  */
0215 void __init pxa_timer_nodt_init(int irq, void __iomem *base)
0216 {
0217     struct clk *clk;
0218
0219     timer_base = base;
0220     clk = clk_get(NULL, "OSTIMER0");
0221     if (clk && !IS_ERR(clk)) {
0222         clk_prepare_enable(clk);
0223         pxa_timer_common_init(irq, clk_get_rate(clk));
0224     } else {
0225         pr_crit("%s: unable to get clk\n", __func__);
0226     }
0227 }