drivers/clocksource/timer-oxnas-rps.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * drivers/clocksource/timer-oxnas-rps.c
0004  *
0005  * Copyright (C) 2009 Oxford Semiconductor Ltd
0006  * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
0007  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
0008  */
0009
0010 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0011
0012 #include <linux/init.h>
0013 #include <linux/irq.h>
0014 #include <linux/io.h>
0015 #include <linux/clk.h>
0016 #include <linux/slab.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/of_irq.h>
0019 #include <linux/of_address.h>
0020 #include <linux/clockchips.h>
0021 #include <linux/sched_clock.h>
0022
0023 /* TIMER1 used as tick
0024  * TIMER2 used as clocksource
0025  */
0026
0027 /* Registers definitions */
0028
0029 #define TIMER_LOAD_REG      0x0
0030 #define TIMER_CURR_REG      0x4
0031 #define TIMER_CTRL_REG      0x8
0032 #define TIMER_CLRINT_REG    0xC
0033
0034 #define TIMER_BITS      24
0035
0036 #define TIMER_MAX_VAL       (BIT(TIMER_BITS) - 1)
0037
0038 #define TIMER_PERIODIC      BIT(6)
0039 #define TIMER_ENABLE        BIT(7)
0040
0041 #define TIMER_DIV1      (0)
0042 #define TIMER_DIV16     (1 << 2)
0043 #define TIMER_DIV256        (2 << 2)
0044
0045 #define TIMER1_REG_OFFSET   0
0046 #define TIMER2_REG_OFFSET   0x20
0047
0048 /* Clockevent & Clocksource data */
0049
0050 struct oxnas_rps_timer {
0051     struct clock_event_device clkevent;
0052     void __iomem *clksrc_base;
0053     void __iomem *clkevt_base;
0054     unsigned long timer_period;
0055     unsigned int timer_prescaler;
0056     struct clk *clk;
0057     int irq;
0058 };
0059
0060 static irqreturn_t oxnas_rps_timer_irq(int irq, void *dev_id)
0061 {
0062     struct oxnas_rps_timer *rps = dev_id;
0063
0064     writel_relaxed(0, rps->clkevt_base + TIMER_CLRINT_REG);
0065
0066     rps->clkevent.event_handler(&rps->clkevent);
0067
0068     return IRQ_HANDLED;
0069 }
0070
0071 static void oxnas_rps_timer_config(struct oxnas_rps_timer *rps,
0072                    unsigned long period,
0073                    unsigned int periodic)
0074 {
0075     uint32_t cfg = rps->timer_prescaler;
0076
0077     if (period)
0078         cfg |= TIMER_ENABLE;
0079
0080     if (periodic)
0081         cfg |= TIMER_PERIODIC;
0082
0083     writel_relaxed(period, rps->clkevt_base + TIMER_LOAD_REG);
0084     writel_relaxed(cfg, rps->clkevt_base + TIMER_CTRL_REG);
0085 }
0086
0087 static int oxnas_rps_timer_shutdown(struct clock_event_device *evt)
0088 {
0089     struct oxnas_rps_timer *rps =
0090         container_of(evt, struct oxnas_rps_timer, clkevent);
0091
0092     oxnas_rps_timer_config(rps, 0, 0);
0093
0094     return 0;
0095 }
0096
0097 static int oxnas_rps_timer_set_periodic(struct clock_event_device *evt)
0098 {
0099     struct oxnas_rps_timer *rps =
0100         container_of(evt, struct oxnas_rps_timer, clkevent);
0101
0102     oxnas_rps_timer_config(rps, rps->timer_period, 1);
0103
0104     return 0;
0105 }
0106
0107 static int oxnas_rps_timer_set_oneshot(struct clock_event_device *evt)
0108 {
0109     struct oxnas_rps_timer *rps =
0110         container_of(evt, struct oxnas_rps_timer, clkevent);
0111
0112     oxnas_rps_timer_config(rps, rps->timer_period, 0);
0113
0114     return 0;
0115 }
0116
0117 static int oxnas_rps_timer_next_event(unsigned long delta,
0118                 struct clock_event_device *evt)
0119 {
0120     struct oxnas_rps_timer *rps =
0121         container_of(evt, struct oxnas_rps_timer, clkevent);
0122
0123     oxnas_rps_timer_config(rps, delta, 0);
0124
0125     return 0;
0126 }
0127
0128 static int __init oxnas_rps_clockevent_init(struct oxnas_rps_timer *rps)
0129 {
0130     ulong clk_rate = clk_get_rate(rps->clk);
0131     ulong timer_rate;
0132
0133     /* Start with prescaler 1 */
0134     rps->timer_prescaler = TIMER_DIV1;
0135     rps->timer_period = DIV_ROUND_UP(clk_rate, HZ);
0136     timer_rate = clk_rate;
0137
0138     if (rps->timer_period > TIMER_MAX_VAL) {
0139         rps->timer_prescaler = TIMER_DIV16;
0140         timer_rate = clk_rate / 16;
0141         rps->timer_period = DIV_ROUND_UP(timer_rate, HZ);
0142     }
0143     if (rps->timer_period > TIMER_MAX_VAL) {
0144         rps->timer_prescaler = TIMER_DIV256;
0145         timer_rate = clk_rate / 256;
0146         rps->timer_period = DIV_ROUND_UP(timer_rate, HZ);
0147     }
0148
0149     rps->clkevent.name = "oxnas-rps";
0150     rps->clkevent.features = CLOCK_EVT_FEAT_PERIODIC |
0151                  CLOCK_EVT_FEAT_ONESHOT |
0152                  CLOCK_EVT_FEAT_DYNIRQ;
0153     rps->clkevent.tick_resume = oxnas_rps_timer_shutdown;
0154     rps->clkevent.set_state_shutdown = oxnas_rps_timer_shutdown;
0155     rps->clkevent.set_state_periodic = oxnas_rps_timer_set_periodic;
0156     rps->clkevent.set_state_oneshot = oxnas_rps_timer_set_oneshot;
0157     rps->clkevent.set_next_event = oxnas_rps_timer_next_event;
0158     rps->clkevent.rating = 200;
0159     rps->clkevent.cpumask = cpu_possible_mask;
0160     rps->clkevent.irq = rps->irq;
0161     clockevents_config_and_register(&rps->clkevent,
0162                     timer_rate,
0163                     1,
0164                     TIMER_MAX_VAL);
0165
0166     pr_info("Registered clock event rate %luHz prescaler %x period %lu\n",
0167             clk_rate,
0168             rps->timer_prescaler,
0169             rps->timer_period);
0170
0171     return 0;
0172 }
0173
0174 /* Clocksource */
0175
0176 static void __iomem *timer_sched_base;
0177
0178 static u64 notrace oxnas_rps_read_sched_clock(void)
0179 {
0180     return ~readl_relaxed(timer_sched_base);
0181 }
0182
0183 static int __init oxnas_rps_clocksource_init(struct oxnas_rps_timer *rps)
0184 {
0185     ulong clk_rate = clk_get_rate(rps->clk);
0186     int ret;
0187
0188     /* use prescale 16 */
0189     clk_rate = clk_rate / 16;
0190
0191     writel_relaxed(TIMER_MAX_VAL, rps->clksrc_base + TIMER_LOAD_REG);
0192     writel_relaxed(TIMER_PERIODIC | TIMER_ENABLE | TIMER_DIV16,
0193             rps->clksrc_base + TIMER_CTRL_REG);
0194
0195     timer_sched_base = rps->clksrc_base + TIMER_CURR_REG;
0196     sched_clock_register(oxnas_rps_read_sched_clock,
0197                  TIMER_BITS, clk_rate);
0198     ret = clocksource_mmio_init(timer_sched_base,
0199                     "oxnas_rps_clocksource_timer",
0200                     clk_rate, 250, TIMER_BITS,
0201                     clocksource_mmio_readl_down);
0202     if (WARN_ON(ret)) {
0203         pr_err("can't register clocksource\n");
0204         return ret;
0205     }
0206
0207     pr_info("Registered clocksource rate %luHz\n", clk_rate);
0208
0209     return 0;
0210 }
0211
0212 static int __init oxnas_rps_timer_init(struct device_node *np)
0213 {
0214     struct oxnas_rps_timer *rps;
0215     void __iomem *base;
0216     int ret;
0217
0218     rps = kzalloc(sizeof(*rps), GFP_KERNEL);
0219     if (!rps)
0220         return -ENOMEM;
0221
0222     rps->clk = of_clk_get(np, 0);
0223     if (IS_ERR(rps->clk)) {
0224         ret = PTR_ERR(rps->clk);
0225         goto err_alloc;
0226     }
0227
0228     ret = clk_prepare_enable(rps->clk);
0229     if (ret)
0230         goto err_clk;
0231
0232     base = of_iomap(np, 0);
0233     if (!base) {
0234         ret = -ENXIO;
0235         goto err_clk_prepare;
0236     }
0237
0238     rps->irq = irq_of_parse_and_map(np, 0);
0239     if (!rps->irq) {
0240         ret = -EINVAL;
0241         goto err_iomap;
0242     }
0243
0244     rps->clkevt_base = base + TIMER1_REG_OFFSET;
0245     rps->clksrc_base = base + TIMER2_REG_OFFSET;
0246
0247     /* Disable timers */
0248     writel_relaxed(0, rps->clkevt_base + TIMER_CTRL_REG);
0249     writel_relaxed(0, rps->clksrc_base + TIMER_CTRL_REG);
0250     writel_relaxed(0, rps->clkevt_base + TIMER_LOAD_REG);
0251     writel_relaxed(0, rps->clksrc_base + TIMER_LOAD_REG);
0252     writel_relaxed(0, rps->clkevt_base + TIMER_CLRINT_REG);
0253     writel_relaxed(0, rps->clksrc_base + TIMER_CLRINT_REG);
0254
0255     ret = request_irq(rps->irq, oxnas_rps_timer_irq,
0256               IRQF_TIMER | IRQF_IRQPOLL,
0257               "rps-timer", rps);
0258     if (ret)
0259         goto err_iomap;
0260
0261     ret = oxnas_rps_clocksource_init(rps);
0262     if (ret)
0263         goto err_irqreq;
0264
0265     ret = oxnas_rps_clockevent_init(rps);
0266     if (ret)
0267         goto err_irqreq;
0268
0269     return 0;
0270
0271 err_irqreq:
0272     free_irq(rps->irq, rps);
0273 err_iomap:
0274     iounmap(base);
0275 err_clk_prepare:
0276     clk_disable_unprepare(rps->clk);
0277 err_clk:
0278     clk_put(rps->clk);
0279 err_alloc:
0280     kfree(rps);
0281
0282     return ret;
0283 }
0284
0285 TIMER_OF_DECLARE(ox810se_rps,
0286                "oxsemi,ox810se-rps-timer", oxnas_rps_timer_init);
0287 TIMER_OF_DECLARE(ox820_rps,
0288                "oxsemi,ox820-rps-timer", oxnas_rps_timer_init);