drivers/clocksource/timer-owl.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Actions Semi Owl timer
0004  *
0005  * Copyright 2012 Actions Semi Inc.
0006  * Author: Actions Semi, Inc.
0007  *
0008  * Copyright (c) 2017 SUSE Linux GmbH
0009  * Author: Andreas Färber
0010  */
0011
0012 #include <linux/clk.h>
0013 #include <linux/clockchips.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/irq.h>
0016 #include <linux/irqreturn.h>
0017 #include <linux/sched_clock.h>
0018 #include <linux/of.h>
0019 #include <linux/of_address.h>
0020 #include <linux/of_irq.h>
0021
0022 #define OWL_Tx_CTL      0x0
0023 #define OWL_Tx_CMP      0x4
0024 #define OWL_Tx_VAL      0x8
0025
0026 #define OWL_Tx_CTL_PD       BIT(0)
0027 #define OWL_Tx_CTL_INTEN    BIT(1)
0028 #define OWL_Tx_CTL_EN       BIT(2)
0029
0030 static void __iomem *owl_timer_base;
0031 static void __iomem *owl_clksrc_base;
0032 static void __iomem *owl_clkevt_base;
0033
0034 static inline void owl_timer_reset(void __iomem *base)
0035 {
0036     writel(0, base + OWL_Tx_CTL);
0037     writel(0, base + OWL_Tx_VAL);
0038     writel(0, base + OWL_Tx_CMP);
0039 }
0040
0041 static inline void owl_timer_set_enabled(void __iomem *base, bool enabled)
0042 {
0043     u32 ctl = readl(base + OWL_Tx_CTL);
0044
0045     /* PD bit is cleared when set */
0046     ctl &= ~OWL_Tx_CTL_PD;
0047
0048     if (enabled)
0049         ctl |= OWL_Tx_CTL_EN;
0050     else
0051         ctl &= ~OWL_Tx_CTL_EN;
0052
0053     writel(ctl, base + OWL_Tx_CTL);
0054 }
0055
0056 static u64 notrace owl_timer_sched_read(void)
0057 {
0058     return (u64)readl(owl_clksrc_base + OWL_Tx_VAL);
0059 }
0060
0061 static int owl_timer_set_state_shutdown(struct clock_event_device *evt)
0062 {
0063     owl_timer_set_enabled(owl_clkevt_base, false);
0064
0065     return 0;
0066 }
0067
0068 static int owl_timer_set_state_oneshot(struct clock_event_device *evt)
0069 {
0070     owl_timer_reset(owl_clkevt_base);
0071
0072     return 0;
0073 }
0074
0075 static int owl_timer_tick_resume(struct clock_event_device *evt)
0076 {
0077     return 0;
0078 }
0079
0080 static int owl_timer_set_next_event(unsigned long evt,
0081                     struct clock_event_device *ev)
0082 {
0083     void __iomem *base = owl_clkevt_base;
0084
0085     owl_timer_set_enabled(base, false);
0086     writel(OWL_Tx_CTL_INTEN, base + OWL_Tx_CTL);
0087     writel(0, base + OWL_Tx_VAL);
0088     writel(evt, base + OWL_Tx_CMP);
0089     owl_timer_set_enabled(base, true);
0090
0091     return 0;
0092 }
0093
0094 static struct clock_event_device owl_clockevent = {
0095     .name           = "owl_tick",
0096     .rating         = 200,
0097     .features       = CLOCK_EVT_FEAT_ONESHOT |
0098                   CLOCK_EVT_FEAT_DYNIRQ,
0099     .set_state_shutdown = owl_timer_set_state_shutdown,
0100     .set_state_oneshot  = owl_timer_set_state_oneshot,
0101     .tick_resume        = owl_timer_tick_resume,
0102     .set_next_event     = owl_timer_set_next_event,
0103 };
0104
0105 static irqreturn_t owl_timer1_interrupt(int irq, void *dev_id)
0106 {
0107     struct clock_event_device *evt = (struct clock_event_device *)dev_id;
0108
0109     writel(OWL_Tx_CTL_PD, owl_clkevt_base + OWL_Tx_CTL);
0110
0111     evt->event_handler(evt);
0112
0113     return IRQ_HANDLED;
0114 }
0115
0116 static int __init owl_timer_init(struct device_node *node)
0117 {
0118     struct clk *clk;
0119     unsigned long rate;
0120     int timer1_irq, ret;
0121
0122     owl_timer_base = of_io_request_and_map(node, 0, "owl-timer");
0123     if (IS_ERR(owl_timer_base)) {
0124         pr_err("Can't map timer registers\n");
0125         return PTR_ERR(owl_timer_base);
0126     }
0127
0128     owl_clksrc_base = owl_timer_base + 0x08;
0129     owl_clkevt_base = owl_timer_base + 0x14;
0130
0131     timer1_irq = of_irq_get_byname(node, "timer1");
0132     if (timer1_irq <= 0) {
0133         pr_err("Can't parse timer1 IRQ\n");
0134         return -EINVAL;
0135     }
0136
0137     clk = of_clk_get(node, 0);
0138     if (IS_ERR(clk)) {
0139         ret = PTR_ERR(clk);
0140         pr_err("Failed to get clock for clocksource (%d)\n", ret);
0141         return ret;
0142     }
0143
0144     rate = clk_get_rate(clk);
0145
0146     owl_timer_reset(owl_clksrc_base);
0147     owl_timer_set_enabled(owl_clksrc_base, true);
0148
0149     sched_clock_register(owl_timer_sched_read, 32, rate);
0150     ret = clocksource_mmio_init(owl_clksrc_base + OWL_Tx_VAL, node->name,
0151                     rate, 200, 32, clocksource_mmio_readl_up);
0152     if (ret) {
0153         pr_err("Failed to register clocksource (%d)\n", ret);
0154         return ret;
0155     }
0156
0157     owl_timer_reset(owl_clkevt_base);
0158
0159     ret = request_irq(timer1_irq, owl_timer1_interrupt, IRQF_TIMER,
0160               "owl-timer", &owl_clockevent);
0161     if (ret) {
0162         pr_err("failed to request irq %d\n", timer1_irq);
0163         return ret;
0164     }
0165
0166     owl_clockevent.cpumask = cpumask_of(0);
0167     owl_clockevent.irq = timer1_irq;
0168
0169     clockevents_config_and_register(&owl_clockevent, rate,
0170                     0xf, 0xffffffff);
0171
0172     return 0;
0173 }
0174 TIMER_OF_DECLARE(owl_s500, "actions,s500-timer", owl_timer_init);
0175 TIMER_OF_DECLARE(owl_s700, "actions,s700-timer", owl_timer_init);
0176 TIMER_OF_DECLARE(owl_s900, "actions,s900-timer", owl_timer_init);