drivers/clocksource/timer-msc313e.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * MStar timer driver
0004  *
0005  * Copyright (C) 2021 Daniel Palmer
0006  * Copyright (C) 2021 Romain Perier
0007  *
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/clockchips.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/irq.h>
0014 #include <linux/irqreturn.h>
0015 #include <linux/sched_clock.h>
0016 #include <linux/of.h>
0017 #include <linux/of_address.h>
0018 #include <linux/of_irq.h>
0019
0020 #ifdef CONFIG_ARM
0021 #include <linux/delay.h>
0022 #endif
0023
0024 #include "timer-of.h"
0025
0026 #define TIMER_NAME "msc313e_timer"
0027
0028 #define MSC313E_REG_CTRL        0x00
0029 #define MSC313E_REG_CTRL_TIMER_EN   BIT(0)
0030 #define MSC313E_REG_CTRL_TIMER_TRIG BIT(1)
0031 #define MSC313E_REG_CTRL_TIMER_INT_EN   BIT(8)
0032 #define MSC313E_REG_TIMER_MAX_LOW   0x08
0033 #define MSC313E_REG_TIMER_MAX_HIGH  0x0c
0034 #define MSC313E_REG_COUNTER_LOW     0x10
0035 #define MSC313E_REG_COUNTER_HIGH    0x14
0036 #define MSC313E_REG_TIMER_DIVIDE    0x18
0037
0038 #define MSC313E_CLK_DIVIDER     9
0039 #define TIMER_SYNC_TICKS        3
0040
0041 #ifdef CONFIG_ARM
0042 struct msc313e_delay {
0043     void __iomem *base;
0044     struct delay_timer delay;
0045 };
0046 static struct msc313e_delay msc313e_delay;
0047 #endif
0048
0049 static void __iomem *msc313e_clksrc;
0050
0051 static void msc313e_timer_stop(void __iomem *base)
0052 {
0053     writew(0, base + MSC313E_REG_CTRL);
0054 }
0055
0056 static void msc313e_timer_start(void __iomem *base, bool periodic)
0057 {
0058     u16 reg;
0059
0060     reg = readw(base + MSC313E_REG_CTRL);
0061     if (periodic)
0062         reg |= MSC313E_REG_CTRL_TIMER_EN;
0063     else
0064         reg |= MSC313E_REG_CTRL_TIMER_TRIG;
0065     writew(reg | MSC313E_REG_CTRL_TIMER_INT_EN, base + MSC313E_REG_CTRL);
0066 }
0067
0068 static void msc313e_timer_setup(void __iomem *base, unsigned long delay)
0069 {
0070     unsigned long flags;
0071
0072     local_irq_save(flags);
0073     writew(delay >> 16, base + MSC313E_REG_TIMER_MAX_HIGH);
0074     writew(delay & 0xffff, base + MSC313E_REG_TIMER_MAX_LOW);
0075     local_irq_restore(flags);
0076 }
0077
0078 static unsigned long msc313e_timer_current_value(void __iomem *base)
0079 {
0080     unsigned long flags;
0081     u16 l, h;
0082
0083     local_irq_save(flags);
0084     l = readw(base + MSC313E_REG_COUNTER_LOW);
0085     h = readw(base + MSC313E_REG_COUNTER_HIGH);
0086     local_irq_restore(flags);
0087
0088     return (((u32)h) << 16 | l);
0089 }
0090
0091 static int msc313e_timer_clkevt_shutdown(struct clock_event_device *evt)
0092 {
0093     struct timer_of *timer = to_timer_of(evt);
0094
0095     msc313e_timer_stop(timer_of_base(timer));
0096
0097     return 0;
0098 }
0099
0100 static int msc313e_timer_clkevt_set_oneshot(struct clock_event_device *evt)
0101 {
0102     struct timer_of *timer = to_timer_of(evt);
0103
0104     msc313e_timer_stop(timer_of_base(timer));
0105     msc313e_timer_start(timer_of_base(timer), false);
0106
0107     return 0;
0108 }
0109
0110 static int msc313e_timer_clkevt_set_periodic(struct clock_event_device *evt)
0111 {
0112     struct timer_of *timer = to_timer_of(evt);
0113
0114     msc313e_timer_stop(timer_of_base(timer));
0115     msc313e_timer_setup(timer_of_base(timer), timer_of_period(timer));
0116     msc313e_timer_start(timer_of_base(timer), true);
0117
0118     return 0;
0119 }
0120
0121 static int msc313e_timer_clkevt_next_event(unsigned long evt, struct clock_event_device *clkevt)
0122 {
0123     struct timer_of *timer = to_timer_of(clkevt);
0124
0125     msc313e_timer_stop(timer_of_base(timer));
0126     msc313e_timer_setup(timer_of_base(timer), evt);
0127     msc313e_timer_start(timer_of_base(timer), false);
0128
0129     return 0;
0130 }
0131
0132 static irqreturn_t msc313e_timer_clkevt_irq(int irq, void *dev_id)
0133 {
0134     struct clock_event_device *evt = dev_id;
0135
0136     evt->event_handler(evt);
0137
0138     return IRQ_HANDLED;
0139 }
0140
0141 static u64 msc313e_timer_clksrc_read(struct clocksource *cs)
0142 {
0143     return msc313e_timer_current_value(msc313e_clksrc) & cs->mask;
0144 }
0145
0146 #ifdef CONFIG_ARM
0147 static unsigned long msc313e_read_delay_timer_read(void)
0148 {
0149     return msc313e_timer_current_value(msc313e_delay.base);
0150 }
0151 #endif
0152
0153 static u64 msc313e_timer_sched_clock_read(void)
0154 {
0155     return msc313e_timer_current_value(msc313e_clksrc);
0156 }
0157
0158 static struct clock_event_device msc313e_clkevt = {
0159     .name = TIMER_NAME,
0160     .rating = 300,
0161     .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
0162     .set_state_shutdown = msc313e_timer_clkevt_shutdown,
0163     .set_state_periodic = msc313e_timer_clkevt_set_periodic,
0164     .set_state_oneshot = msc313e_timer_clkevt_set_oneshot,
0165     .tick_resume = msc313e_timer_clkevt_shutdown,
0166     .set_next_event = msc313e_timer_clkevt_next_event,
0167 };
0168
0169 static int __init msc313e_clkevt_init(struct device_node *np)
0170 {
0171     int ret;
0172     struct timer_of *to;
0173
0174     to = kzalloc(sizeof(*to), GFP_KERNEL);
0175     if (!to)
0176         return -ENOMEM;
0177
0178     to->flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE;
0179     to->of_irq.handler = msc313e_timer_clkevt_irq;
0180     ret = timer_of_init(np, to);
0181     if (ret)
0182         return ret;
0183
0184     if (of_device_is_compatible(np, "sstar,ssd20xd-timer")) {
0185         to->of_clk.rate = clk_get_rate(to->of_clk.clk) / MSC313E_CLK_DIVIDER;
0186         to->of_clk.period = DIV_ROUND_UP(to->of_clk.rate, HZ);
0187         writew(MSC313E_CLK_DIVIDER - 1, timer_of_base(to) + MSC313E_REG_TIMER_DIVIDE);
0188     }
0189
0190     msc313e_clkevt.cpumask = cpu_possible_mask;
0191     msc313e_clkevt.irq = to->of_irq.irq;
0192     to->clkevt = msc313e_clkevt;
0193
0194     clockevents_config_and_register(&to->clkevt, timer_of_rate(to),
0195                     TIMER_SYNC_TICKS, 0xffffffff);
0196     return 0;
0197 }
0198
0199 static int __init msc313e_clksrc_init(struct device_node *np)
0200 {
0201     struct timer_of to = { 0 };
0202     int ret;
0203     u16 reg;
0204
0205     to.flags = TIMER_OF_BASE | TIMER_OF_CLOCK;
0206     ret = timer_of_init(np, &to);
0207     if (ret)
0208         return ret;
0209
0210     msc313e_clksrc = timer_of_base(&to);
0211     reg = readw(msc313e_clksrc + MSC313E_REG_CTRL);
0212     reg |= MSC313E_REG_CTRL_TIMER_EN;
0213     writew(reg, msc313e_clksrc + MSC313E_REG_CTRL);
0214
0215 #ifdef CONFIG_ARM
0216     msc313e_delay.base = timer_of_base(&to);
0217     msc313e_delay.delay.read_current_timer = msc313e_read_delay_timer_read;
0218     msc313e_delay.delay.freq = timer_of_rate(&to);
0219
0220     register_current_timer_delay(&msc313e_delay.delay);
0221 #endif
0222
0223     sched_clock_register(msc313e_timer_sched_clock_read, 32, timer_of_rate(&to));
0224     return clocksource_mmio_init(timer_of_base(&to), TIMER_NAME, timer_of_rate(&to), 300, 32,
0225                      msc313e_timer_clksrc_read);
0226 }
0227
0228 static int __init msc313e_timer_init(struct device_node *np)
0229 {
0230     int ret = 0;
0231     static int num_called;
0232
0233     switch (num_called) {
0234     case 0:
0235         ret = msc313e_clksrc_init(np);
0236         if (ret)
0237             return ret;
0238         break;
0239
0240     default:
0241         ret = msc313e_clkevt_init(np);
0242         if (ret)
0243             return ret;
0244         break;
0245     }
0246
0247     num_called++;
0248
0249     return 0;
0250 }
0251
0252 TIMER_OF_DECLARE(msc313, "mstar,msc313e-timer", msc313e_timer_init);
0253 TIMER_OF_DECLARE(ssd20xd, "sstar,ssd20xd-timer", msc313e_timer_init);