drivers/clocksource/timer-lpc32xx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Clocksource driver for NXP LPC32xx/18xx/43xx timer
0004  *
0005  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
0006  *
0007  * Based on:
0008  * time-efm32 Copyright (C) 2013 Pengutronix
0009  * mach-lpc32xx/timer.c Copyright (C) 2009 - 2010 NXP Semiconductors
0010  */
0011
0012 #define pr_fmt(fmt) "%s: " fmt, __func__
0013
0014 #include <linux/clk.h>
0015 #include <linux/clockchips.h>
0016 #include <linux/clocksource.h>
0017 #include <linux/delay.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/irq.h>
0020 #include <linux/kernel.h>
0021 #include <linux/of.h>
0022 #include <linux/of_address.h>
0023 #include <linux/of_irq.h>
0024 #include <linux/sched_clock.h>
0025
0026 #define LPC32XX_TIMER_IR        0x000
0027 #define  LPC32XX_TIMER_IR_MR0INT    BIT(0)
0028 #define LPC32XX_TIMER_TCR       0x004
0029 #define  LPC32XX_TIMER_TCR_CEN      BIT(0)
0030 #define  LPC32XX_TIMER_TCR_CRST     BIT(1)
0031 #define LPC32XX_TIMER_TC        0x008
0032 #define LPC32XX_TIMER_PR        0x00c
0033 #define LPC32XX_TIMER_MCR       0x014
0034 #define  LPC32XX_TIMER_MCR_MR0I     BIT(0)
0035 #define  LPC32XX_TIMER_MCR_MR0R     BIT(1)
0036 #define  LPC32XX_TIMER_MCR_MR0S     BIT(2)
0037 #define LPC32XX_TIMER_MR0       0x018
0038 #define LPC32XX_TIMER_CTCR      0x070
0039
0040 struct lpc32xx_clock_event_ddata {
0041     struct clock_event_device evtdev;
0042     void __iomem *base;
0043     u32 ticks_per_jiffy;
0044 };
0045
0046 /* Needed for the sched clock */
0047 static void __iomem *clocksource_timer_counter;
0048
0049 static u64 notrace lpc32xx_read_sched_clock(void)
0050 {
0051     return readl(clocksource_timer_counter);
0052 }
0053
0054 static unsigned long lpc32xx_delay_timer_read(void)
0055 {
0056     return readl(clocksource_timer_counter);
0057 }
0058
0059 static struct delay_timer lpc32xx_delay_timer = {
0060     .read_current_timer = lpc32xx_delay_timer_read,
0061 };
0062
0063 static int lpc32xx_clkevt_next_event(unsigned long delta,
0064                      struct clock_event_device *evtdev)
0065 {
0066     struct lpc32xx_clock_event_ddata *ddata =
0067         container_of(evtdev, struct lpc32xx_clock_event_ddata, evtdev);
0068
0069     /*
0070      * Place timer in reset and program the delta in the match
0071      * channel 0 (MR0). When the timer counter matches the value
0072      * in MR0 register the match will trigger an interrupt.
0073      * After setup the timer is released from reset and enabled.
0074      */
0075     writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR);
0076     writel_relaxed(delta, ddata->base + LPC32XX_TIMER_MR0);
0077     writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR);
0078
0079     return 0;
0080 }
0081
0082 static int lpc32xx_clkevt_shutdown(struct clock_event_device *evtdev)
0083 {
0084     struct lpc32xx_clock_event_ddata *ddata =
0085         container_of(evtdev, struct lpc32xx_clock_event_ddata, evtdev);
0086
0087     /* Disable the timer */
0088     writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR);
0089
0090     return 0;
0091 }
0092
0093 static int lpc32xx_clkevt_oneshot(struct clock_event_device *evtdev)
0094 {
0095     struct lpc32xx_clock_event_ddata *ddata =
0096         container_of(evtdev, struct lpc32xx_clock_event_ddata, evtdev);
0097
0098     /*
0099      * When using oneshot, we must also disable the timer
0100      * to wait for the first call to set_next_event().
0101      */
0102     writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR);
0103
0104     /* Enable interrupt, reset on match and stop on match (MCR). */
0105     writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R |
0106                LPC32XX_TIMER_MCR_MR0S, ddata->base + LPC32XX_TIMER_MCR);
0107     return 0;
0108 }
0109
0110 static int lpc32xx_clkevt_periodic(struct clock_event_device *evtdev)
0111 {
0112     struct lpc32xx_clock_event_ddata *ddata =
0113         container_of(evtdev, struct lpc32xx_clock_event_ddata, evtdev);
0114
0115     /* Enable interrupt and reset on match. */
0116     writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R,
0117                ddata->base + LPC32XX_TIMER_MCR);
0118
0119     /*
0120      * Place timer in reset and program the delta in the match
0121      * channel 0 (MR0).
0122      */
0123     writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR);
0124     writel_relaxed(ddata->ticks_per_jiffy, ddata->base + LPC32XX_TIMER_MR0);
0125     writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR);
0126
0127     return 0;
0128 }
0129
0130 static irqreturn_t lpc32xx_clock_event_handler(int irq, void *dev_id)
0131 {
0132     struct lpc32xx_clock_event_ddata *ddata = dev_id;
0133
0134     /* Clear match on channel 0 */
0135     writel_relaxed(LPC32XX_TIMER_IR_MR0INT, ddata->base + LPC32XX_TIMER_IR);
0136
0137     ddata->evtdev.event_handler(&ddata->evtdev);
0138
0139     return IRQ_HANDLED;
0140 }
0141
0142 static struct lpc32xx_clock_event_ddata lpc32xx_clk_event_ddata = {
0143     .evtdev = {
0144         .name           = "lpc3220 clockevent",
0145         .features       = CLOCK_EVT_FEAT_ONESHOT |
0146                       CLOCK_EVT_FEAT_PERIODIC,
0147         .rating         = 300,
0148         .set_next_event     = lpc32xx_clkevt_next_event,
0149         .set_state_shutdown = lpc32xx_clkevt_shutdown,
0150         .set_state_oneshot  = lpc32xx_clkevt_oneshot,
0151         .set_state_periodic = lpc32xx_clkevt_periodic,
0152     },
0153 };
0154
0155 static int __init lpc32xx_clocksource_init(struct device_node *np)
0156 {
0157     void __iomem *base;
0158     unsigned long rate;
0159     struct clk *clk;
0160     int ret;
0161
0162     clk = of_clk_get_by_name(np, "timerclk");
0163     if (IS_ERR(clk)) {
0164         pr_err("clock get failed (%ld)\n", PTR_ERR(clk));
0165         return PTR_ERR(clk);
0166     }
0167
0168     ret = clk_prepare_enable(clk);
0169     if (ret) {
0170         pr_err("clock enable failed (%d)\n", ret);
0171         goto err_clk_enable;
0172     }
0173
0174     base = of_iomap(np, 0);
0175     if (!base) {
0176         pr_err("unable to map registers\n");
0177         ret = -EADDRNOTAVAIL;
0178         goto err_iomap;
0179     }
0180
0181     /*
0182      * Disable and reset timer then set it to free running timer
0183      * mode (CTCR) with no prescaler (PR) or match operations (MCR).
0184      * After setup the timer is released from reset and enabled.
0185      */
0186     writel_relaxed(LPC32XX_TIMER_TCR_CRST, base + LPC32XX_TIMER_TCR);
0187     writel_relaxed(0, base + LPC32XX_TIMER_PR);
0188     writel_relaxed(0, base + LPC32XX_TIMER_MCR);
0189     writel_relaxed(0, base + LPC32XX_TIMER_CTCR);
0190     writel_relaxed(LPC32XX_TIMER_TCR_CEN, base + LPC32XX_TIMER_TCR);
0191
0192     rate = clk_get_rate(clk);
0193     ret = clocksource_mmio_init(base + LPC32XX_TIMER_TC, "lpc3220 timer",
0194                     rate, 300, 32, clocksource_mmio_readl_up);
0195     if (ret) {
0196         pr_err("failed to init clocksource (%d)\n", ret);
0197         goto err_clocksource_init;
0198     }
0199
0200     clocksource_timer_counter = base + LPC32XX_TIMER_TC;
0201     lpc32xx_delay_timer.freq = rate;
0202     register_current_timer_delay(&lpc32xx_delay_timer);
0203     sched_clock_register(lpc32xx_read_sched_clock, 32, rate);
0204
0205     return 0;
0206
0207 err_clocksource_init:
0208     iounmap(base);
0209 err_iomap:
0210     clk_disable_unprepare(clk);
0211 err_clk_enable:
0212     clk_put(clk);
0213     return ret;
0214 }
0215
0216 static int __init lpc32xx_clockevent_init(struct device_node *np)
0217 {
0218     void __iomem *base;
0219     unsigned long rate;
0220     struct clk *clk;
0221     int ret, irq;
0222
0223     clk = of_clk_get_by_name(np, "timerclk");
0224     if (IS_ERR(clk)) {
0225         pr_err("clock get failed (%ld)\n", PTR_ERR(clk));
0226         return PTR_ERR(clk);
0227     }
0228
0229     ret = clk_prepare_enable(clk);
0230     if (ret) {
0231         pr_err("clock enable failed (%d)\n", ret);
0232         goto err_clk_enable;
0233     }
0234
0235     base = of_iomap(np, 0);
0236     if (!base) {
0237         pr_err("unable to map registers\n");
0238         ret = -EADDRNOTAVAIL;
0239         goto err_iomap;
0240     }
0241
0242     irq = irq_of_parse_and_map(np, 0);
0243     if (!irq) {
0244         pr_err("get irq failed\n");
0245         ret = -ENOENT;
0246         goto err_irq;
0247     }
0248
0249     /*
0250      * Disable timer and clear any pending interrupt (IR) on match
0251      * channel 0 (MR0). Clear the prescaler as it's not used.
0252      */
0253     writel_relaxed(0, base + LPC32XX_TIMER_TCR);
0254     writel_relaxed(0, base + LPC32XX_TIMER_PR);
0255     writel_relaxed(0, base + LPC32XX_TIMER_CTCR);
0256     writel_relaxed(LPC32XX_TIMER_IR_MR0INT, base + LPC32XX_TIMER_IR);
0257
0258     rate = clk_get_rate(clk);
0259     lpc32xx_clk_event_ddata.base = base;
0260     lpc32xx_clk_event_ddata.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
0261     clockevents_config_and_register(&lpc32xx_clk_event_ddata.evtdev,
0262                     rate, 1, -1);
0263
0264     ret = request_irq(irq, lpc32xx_clock_event_handler,
0265               IRQF_TIMER | IRQF_IRQPOLL, "lpc3220 clockevent",
0266               &lpc32xx_clk_event_ddata);
0267     if (ret) {
0268         pr_err("request irq failed\n");
0269         goto err_irq;
0270     }
0271
0272     return 0;
0273
0274 err_irq:
0275     iounmap(base);
0276 err_iomap:
0277     clk_disable_unprepare(clk);
0278 err_clk_enable:
0279     clk_put(clk);
0280     return ret;
0281 }
0282
0283 /*
0284  * This function asserts that we have exactly one clocksource and one
0285  * clock_event_device in the end.
0286  */
0287 static int __init lpc32xx_timer_init(struct device_node *np)
0288 {
0289     static int has_clocksource, has_clockevent;
0290     int ret = 0;
0291
0292     if (!has_clocksource) {
0293         ret = lpc32xx_clocksource_init(np);
0294         if (!ret) {
0295             has_clocksource = 1;
0296             return 0;
0297         }
0298     }
0299
0300     if (!has_clockevent) {
0301         ret = lpc32xx_clockevent_init(np);
0302         if (!ret) {
0303             has_clockevent = 1;
0304             return 0;
0305         }
0306     }
0307
0308     return ret;
0309 }
0310 TIMER_OF_DECLARE(lpc32xx_timer, "nxp,lpc3220-timer", lpc32xx_timer_init);