drivers/clocksource/timer-keystone.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Keystone broadcast clock-event
0004  *
0005  * Copyright 2013 Texas Instruments, Inc.
0006  *
0007  * Author: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/clockchips.h>
0012 #include <linux/clocksource.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/of_address.h>
0015 #include <linux/of_irq.h>
0016
0017 #define TIMER_NAME          "timer-keystone"
0018
0019 /* Timer register offsets */
0020 #define TIM12               0x10
0021 #define TIM34               0x14
0022 #define PRD12               0x18
0023 #define PRD34               0x1c
0024 #define TCR             0x20
0025 #define TGCR                0x24
0026 #define INTCTLSTAT          0x44
0027
0028 /* Timer register bitfields */
0029 #define TCR_ENAMODE_MASK        0xC0
0030 #define TCR_ENAMODE_ONESHOT_MASK    0x40
0031 #define TCR_ENAMODE_PERIODIC_MASK   0x80
0032
0033 #define TGCR_TIM_UNRESET_MASK       0x03
0034 #define INTCTLSTAT_ENINT_MASK       0x01
0035
0036 /**
0037  * struct keystone_timer: holds timer's data
0038  * @base: timer memory base address
0039  * @hz_period: cycles per HZ period
0040  * @event_dev: event device based on timer
0041  */
0042 static struct keystone_timer {
0043     void __iomem *base;
0044     unsigned long hz_period;
0045     struct clock_event_device event_dev;
0046 } timer;
0047
0048 static inline u32 keystone_timer_readl(unsigned long rg)
0049 {
0050     return readl_relaxed(timer.base + rg);
0051 }
0052
0053 static inline void keystone_timer_writel(u32 val, unsigned long rg)
0054 {
0055     writel_relaxed(val, timer.base + rg);
0056 }
0057
0058 /**
0059  * keystone_timer_barrier: write memory barrier
0060  * use explicit barrier to avoid using readl/writel non relaxed function
0061  * variants, because in our case non relaxed variants hide the true places
0062  * where barrier is needed.
0063  */
0064 static inline void keystone_timer_barrier(void)
0065 {
0066     __iowmb();
0067 }
0068
0069 /**
0070  * keystone_timer_config: configures timer to work in oneshot/periodic modes.
0071  * @ mask: mask of the mode to configure
0072  * @ period: cycles number to configure for
0073  */
0074 static int keystone_timer_config(u64 period, int mask)
0075 {
0076     u32 tcr;
0077     u32 off;
0078
0079     tcr = keystone_timer_readl(TCR);
0080     off = tcr & ~(TCR_ENAMODE_MASK);
0081
0082     /* set enable mode */
0083     tcr |= mask;
0084
0085     /* disable timer */
0086     keystone_timer_writel(off, TCR);
0087     /* here we have to be sure the timer has been disabled */
0088     keystone_timer_barrier();
0089
0090     /* reset counter to zero, set new period */
0091     keystone_timer_writel(0, TIM12);
0092     keystone_timer_writel(0, TIM34);
0093     keystone_timer_writel(period & 0xffffffff, PRD12);
0094     keystone_timer_writel(period >> 32, PRD34);
0095
0096     /*
0097      * enable timer
0098      * here we have to be sure that CNTLO, CNTHI, PRDLO, PRDHI registers
0099      * have been written.
0100      */
0101     keystone_timer_barrier();
0102     keystone_timer_writel(tcr, TCR);
0103     return 0;
0104 }
0105
0106 static void keystone_timer_disable(void)
0107 {
0108     u32 tcr;
0109
0110     tcr = keystone_timer_readl(TCR);
0111
0112     /* disable timer */
0113     tcr &= ~(TCR_ENAMODE_MASK);
0114     keystone_timer_writel(tcr, TCR);
0115 }
0116
0117 static irqreturn_t keystone_timer_interrupt(int irq, void *dev_id)
0118 {
0119     struct clock_event_device *evt = dev_id;
0120
0121     evt->event_handler(evt);
0122     return IRQ_HANDLED;
0123 }
0124
0125 static int keystone_set_next_event(unsigned long cycles,
0126                   struct clock_event_device *evt)
0127 {
0128     return keystone_timer_config(cycles, TCR_ENAMODE_ONESHOT_MASK);
0129 }
0130
0131 static int keystone_shutdown(struct clock_event_device *evt)
0132 {
0133     keystone_timer_disable();
0134     return 0;
0135 }
0136
0137 static int keystone_set_periodic(struct clock_event_device *evt)
0138 {
0139     keystone_timer_config(timer.hz_period, TCR_ENAMODE_PERIODIC_MASK);
0140     return 0;
0141 }
0142
0143 static int __init keystone_timer_init(struct device_node *np)
0144 {
0145     struct clock_event_device *event_dev = &timer.event_dev;
0146     unsigned long rate;
0147     struct clk *clk;
0148     int irq, error;
0149
0150     irq  = irq_of_parse_and_map(np, 0);
0151     if (!irq) {
0152         pr_err("%s: failed to map interrupts\n", __func__);
0153         return -EINVAL;
0154     }
0155
0156     timer.base = of_iomap(np, 0);
0157     if (!timer.base) {
0158         pr_err("%s: failed to map registers\n", __func__);
0159         return -ENXIO;
0160     }
0161
0162     clk = of_clk_get(np, 0);
0163     if (IS_ERR(clk)) {
0164         pr_err("%s: failed to get clock\n", __func__);
0165         iounmap(timer.base);
0166         return PTR_ERR(clk);
0167     }
0168
0169     error = clk_prepare_enable(clk);
0170     if (error) {
0171         pr_err("%s: failed to enable clock\n", __func__);
0172         goto err;
0173     }
0174
0175     rate = clk_get_rate(clk);
0176
0177     /* disable, use internal clock source */
0178     keystone_timer_writel(0, TCR);
0179     /* here we have to be sure the timer has been disabled */
0180     keystone_timer_barrier();
0181
0182     /* reset timer as 64-bit, no pre-scaler, plus features are disabled */
0183     keystone_timer_writel(0, TGCR);
0184
0185     /* unreset timer */
0186     keystone_timer_writel(TGCR_TIM_UNRESET_MASK, TGCR);
0187
0188     /* init counter to zero */
0189     keystone_timer_writel(0, TIM12);
0190     keystone_timer_writel(0, TIM34);
0191
0192     timer.hz_period = DIV_ROUND_UP(rate, HZ);
0193
0194     /* enable timer interrupts */
0195     keystone_timer_writel(INTCTLSTAT_ENINT_MASK, INTCTLSTAT);
0196
0197     error = request_irq(irq, keystone_timer_interrupt, IRQF_TIMER,
0198                 TIMER_NAME, event_dev);
0199     if (error) {
0200         pr_err("%s: failed to setup irq\n", __func__);
0201         goto err;
0202     }
0203
0204     /* setup clockevent */
0205     event_dev->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
0206     event_dev->set_next_event = keystone_set_next_event;
0207     event_dev->set_state_shutdown = keystone_shutdown;
0208     event_dev->set_state_periodic = keystone_set_periodic;
0209     event_dev->set_state_oneshot = keystone_shutdown;
0210     event_dev->cpumask = cpu_possible_mask;
0211     event_dev->owner = THIS_MODULE;
0212     event_dev->name = TIMER_NAME;
0213     event_dev->irq = irq;
0214
0215     clockevents_config_and_register(event_dev, rate, 1, ULONG_MAX);
0216
0217     pr_info("keystone timer clock @%lu Hz\n", rate);
0218     return 0;
0219 err:
0220     clk_put(clk);
0221     iounmap(timer.base);
0222     return error;
0223 }
0224
0225 TIMER_OF_DECLARE(keystone_timer, "ti,keystone-timer",
0226                keystone_timer_init);