drivers/clocksource/timer-ixp4xx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * IXP4 timer driver
0004  * Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org>
0005  *
0006  * Based on arch/arm/mach-ixp4xx/common.c
0007  * Copyright 2002 (C) Intel Corporation
0008  * Copyright 2003-2004 (C) MontaVista, Software, Inc.
0009  * Copyright (C) Deepak Saxena <dsaxena@plexity.net>
0010  */
0011 #include <linux/interrupt.h>
0012 #include <linux/io.h>
0013 #include <linux/clockchips.h>
0014 #include <linux/clocksource.h>
0015 #include <linux/sched_clock.h>
0016 #include <linux/slab.h>
0017 #include <linux/bitops.h>
0018 #include <linux/delay.h>
0019 #include <linux/of_address.h>
0020 #include <linux/of_irq.h>
0021 #include <linux/platform_device.h>
0022
0023 /*
0024  * Constants to make it easy to access Timer Control/Status registers
0025  */
0026 #define IXP4XX_OSTS_OFFSET  0x00  /* Continuous Timestamp */
0027 #define IXP4XX_OST1_OFFSET  0x04  /* Timer 1 Timestamp */
0028 #define IXP4XX_OSRT1_OFFSET 0x08  /* Timer 1 Reload */
0029 #define IXP4XX_OST2_OFFSET  0x0C  /* Timer 2 Timestamp */
0030 #define IXP4XX_OSRT2_OFFSET 0x10  /* Timer 2 Reload */
0031 #define IXP4XX_OSST_OFFSET  0x20  /* Timer Status */
0032
0033 /*
0034  * Timer register values and bit definitions
0035  */
0036 #define IXP4XX_OST_ENABLE       0x00000001
0037 #define IXP4XX_OST_ONE_SHOT     0x00000002
0038 /* Low order bits of reload value ignored */
0039 #define IXP4XX_OST_RELOAD_MASK      0x00000003
0040 #define IXP4XX_OST_DISABLED     0x00000000
0041 #define IXP4XX_OSST_TIMER_1_PEND    0x00000001
0042 #define IXP4XX_OSST_TIMER_2_PEND    0x00000002
0043 #define IXP4XX_OSST_TIMER_TS_PEND   0x00000004
0044 /* Remaining registers are for the watchdog and defined in the watchdog driver */
0045
0046 struct ixp4xx_timer {
0047     void __iomem *base;
0048     u32 latch;
0049     struct clock_event_device clkevt;
0050 #ifdef CONFIG_ARM
0051     struct delay_timer delay_timer;
0052 #endif
0053 };
0054
0055 /*
0056  * A local singleton used by sched_clock and delay timer reads, which are
0057  * fast and stateless
0058  */
0059 static struct ixp4xx_timer *local_ixp4xx_timer;
0060
0061 static inline struct ixp4xx_timer *
0062 to_ixp4xx_timer(struct clock_event_device *evt)
0063 {
0064     return container_of(evt, struct ixp4xx_timer, clkevt);
0065 }
0066
0067 static unsigned long ixp4xx_read_timer(void)
0068 {
0069     return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET);
0070 }
0071
0072 static u64 notrace ixp4xx_read_sched_clock(void)
0073 {
0074     return ixp4xx_read_timer();
0075 }
0076
0077 static u64 ixp4xx_clocksource_read(struct clocksource *c)
0078 {
0079     return ixp4xx_read_timer();
0080 }
0081
0082 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
0083 {
0084     struct ixp4xx_timer *tmr = dev_id;
0085     struct clock_event_device *evt = &tmr->clkevt;
0086
0087     /* Clear Pending Interrupt */
0088     __raw_writel(IXP4XX_OSST_TIMER_1_PEND,
0089              tmr->base + IXP4XX_OSST_OFFSET);
0090
0091     evt->event_handler(evt);
0092
0093     return IRQ_HANDLED;
0094 }
0095
0096 static int ixp4xx_set_next_event(unsigned long cycles,
0097                  struct clock_event_device *evt)
0098 {
0099     struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
0100     u32 val;
0101
0102     val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
0103     /* Keep enable/oneshot bits */
0104     val &= IXP4XX_OST_RELOAD_MASK;
0105     __raw_writel((cycles & ~IXP4XX_OST_RELOAD_MASK) | val,
0106              tmr->base + IXP4XX_OSRT1_OFFSET);
0107
0108     return 0;
0109 }
0110
0111 static int ixp4xx_shutdown(struct clock_event_device *evt)
0112 {
0113     struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
0114     u32 val;
0115
0116     val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
0117     val &= ~IXP4XX_OST_ENABLE;
0118     __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
0119
0120     return 0;
0121 }
0122
0123 static int ixp4xx_set_oneshot(struct clock_event_device *evt)
0124 {
0125     struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
0126
0127     __raw_writel(IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT,
0128              tmr->base + IXP4XX_OSRT1_OFFSET);
0129
0130     return 0;
0131 }
0132
0133 static int ixp4xx_set_periodic(struct clock_event_device *evt)
0134 {
0135     struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
0136     u32 val;
0137
0138     val = tmr->latch & ~IXP4XX_OST_RELOAD_MASK;
0139     val |= IXP4XX_OST_ENABLE;
0140     __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
0141
0142     return 0;
0143 }
0144
0145 static int ixp4xx_resume(struct clock_event_device *evt)
0146 {
0147     struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
0148     u32 val;
0149
0150     val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
0151     val |= IXP4XX_OST_ENABLE;
0152     __raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
0153
0154     return 0;
0155 }
0156
0157 /*
0158  * IXP4xx timer tick
0159  * We use OS timer1 on the CPU for the timer tick and the timestamp
0160  * counter as a source of real clock ticks to account for missed jiffies.
0161  */
0162 static __init int ixp4xx_timer_register(void __iomem *base,
0163                     int timer_irq,
0164                     unsigned int timer_freq)
0165 {
0166     struct ixp4xx_timer *tmr;
0167     int ret;
0168
0169     tmr = kzalloc(sizeof(*tmr), GFP_KERNEL);
0170     if (!tmr)
0171         return -ENOMEM;
0172     tmr->base = base;
0173
0174     /*
0175      * The timer register doesn't allow to specify the two least
0176      * significant bits of the timeout value and assumes them being zero.
0177      * So make sure the latch is the best value with the two least
0178      * significant bits unset.
0179      */
0180     tmr->latch = DIV_ROUND_CLOSEST(timer_freq,
0181                        (IXP4XX_OST_RELOAD_MASK + 1) * HZ)
0182         * (IXP4XX_OST_RELOAD_MASK + 1);
0183
0184     local_ixp4xx_timer = tmr;
0185
0186     /* Reset/disable counter */
0187     __raw_writel(0, tmr->base + IXP4XX_OSRT1_OFFSET);
0188
0189     /* Clear any pending interrupt on timer 1 */
0190     __raw_writel(IXP4XX_OSST_TIMER_1_PEND,
0191              tmr->base + IXP4XX_OSST_OFFSET);
0192
0193     /* Reset time-stamp counter */
0194     __raw_writel(0, tmr->base + IXP4XX_OSTS_OFFSET);
0195
0196     clocksource_mmio_init(NULL, "OSTS", timer_freq, 200, 32,
0197                   ixp4xx_clocksource_read);
0198
0199     tmr->clkevt.name = "ixp4xx timer1";
0200     tmr->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
0201     tmr->clkevt.rating = 200;
0202     tmr->clkevt.set_state_shutdown = ixp4xx_shutdown;
0203     tmr->clkevt.set_state_periodic = ixp4xx_set_periodic;
0204     tmr->clkevt.set_state_oneshot = ixp4xx_set_oneshot;
0205     tmr->clkevt.tick_resume = ixp4xx_resume;
0206     tmr->clkevt.set_next_event = ixp4xx_set_next_event;
0207     tmr->clkevt.cpumask = cpumask_of(0);
0208     tmr->clkevt.irq = timer_irq;
0209     ret = request_irq(timer_irq, ixp4xx_timer_interrupt,
0210               IRQF_TIMER, "IXP4XX-TIMER1", tmr);
0211     if (ret) {
0212         pr_crit("no timer IRQ\n");
0213         return -ENODEV;
0214     }
0215     clockevents_config_and_register(&tmr->clkevt, timer_freq,
0216                     0xf, 0xfffffffe);
0217
0218     sched_clock_register(ixp4xx_read_sched_clock, 32, timer_freq);
0219
0220 #ifdef CONFIG_ARM
0221     /* Also use this timer for delays */
0222     tmr->delay_timer.read_current_timer = ixp4xx_read_timer;
0223     tmr->delay_timer.freq = timer_freq;
0224     register_current_timer_delay(&tmr->delay_timer);
0225 #endif
0226
0227     return 0;
0228 }
0229
0230 static struct platform_device ixp4xx_watchdog_device = {
0231     .name = "ixp4xx-watchdog",
0232     .id = -1,
0233 };
0234
0235 /*
0236  * This probe gets called after the timer is already up and running. The main
0237  * function on this platform is to spawn the watchdog device as a child.
0238  */
0239 static int ixp4xx_timer_probe(struct platform_device *pdev)
0240 {
0241     struct device *dev = &pdev->dev;
0242
0243     /* Pass the base address as platform data and nothing else */
0244     ixp4xx_watchdog_device.dev.platform_data = local_ixp4xx_timer->base;
0245     ixp4xx_watchdog_device.dev.parent = dev;
0246     return platform_device_register(&ixp4xx_watchdog_device);
0247 }
0248
0249 static const struct of_device_id ixp4xx_timer_dt_id[] = {
0250     { .compatible = "intel,ixp4xx-timer", },
0251     { /* sentinel */ },
0252 };
0253
0254 static struct platform_driver ixp4xx_timer_driver = {
0255     .probe  = ixp4xx_timer_probe,
0256     .driver = {
0257         .name = "ixp4xx-timer",
0258         .of_match_table = ixp4xx_timer_dt_id,
0259         .suppress_bind_attrs = true,
0260     },
0261 };
0262 builtin_platform_driver(ixp4xx_timer_driver);
0263
0264 static __init int ixp4xx_of_timer_init(struct device_node *np)
0265 {
0266     void __iomem *base;
0267     int irq;
0268     int ret;
0269
0270     base = of_iomap(np, 0);
0271     if (!base) {
0272         pr_crit("IXP4xx: can't remap timer\n");
0273         return -ENODEV;
0274     }
0275
0276     irq = irq_of_parse_and_map(np, 0);
0277     if (irq <= 0) {
0278         pr_err("Can't parse IRQ\n");
0279         ret = -EINVAL;
0280         goto out_unmap;
0281     }
0282
0283     /* TODO: get some fixed clocks into the device tree */
0284     ret = ixp4xx_timer_register(base, irq, 66666000);
0285     if (ret)
0286         goto out_unmap;
0287     return 0;
0288
0289 out_unmap:
0290     iounmap(base);
0291     return ret;
0292 }
0293 TIMER_OF_DECLARE(ixp4xx, "intel,ixp4xx-timer", ixp4xx_of_timer_init);