drivers/clocksource/timer-gx6605s.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
0003
0004 #include <linux/init.h>
0005 #include <linux/interrupt.h>
0006 #include <linux/sched_clock.h>
0007
0008 #include "timer-of.h"
0009
0010 #define CLKSRC_OFFSET   0x40
0011
0012 #define TIMER_STATUS    0x00
0013 #define TIMER_VALUE 0x04
0014 #define TIMER_CONTRL    0x10
0015 #define TIMER_CONFIG    0x20
0016 #define TIMER_DIV   0x24
0017 #define TIMER_INI   0x28
0018
0019 #define GX6605S_STATUS_CLR  BIT(0)
0020 #define GX6605S_CONTRL_RST  BIT(0)
0021 #define GX6605S_CONTRL_START    BIT(1)
0022 #define GX6605S_CONFIG_EN   BIT(0)
0023 #define GX6605S_CONFIG_IRQ_EN   BIT(1)
0024
0025 static irqreturn_t gx6605s_timer_interrupt(int irq, void *dev)
0026 {
0027     struct clock_event_device *ce = dev;
0028     void __iomem *base = timer_of_base(to_timer_of(ce));
0029
0030     writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS);
0031     writel_relaxed(0, base + TIMER_INI);
0032
0033     ce->event_handler(ce);
0034
0035     return IRQ_HANDLED;
0036 }
0037
0038 static int gx6605s_timer_set_oneshot(struct clock_event_device *ce)
0039 {
0040     void __iomem *base = timer_of_base(to_timer_of(ce));
0041
0042     /* reset and stop counter */
0043     writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
0044
0045     /* enable with irq and start */
0046     writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN,
0047                base + TIMER_CONFIG);
0048
0049     return 0;
0050 }
0051
0052 static int gx6605s_timer_set_next_event(unsigned long delta,
0053                     struct clock_event_device *ce)
0054 {
0055     void __iomem *base = timer_of_base(to_timer_of(ce));
0056
0057     /* use reset to pause timer */
0058     writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
0059
0060     /* config next timeout value */
0061     writel_relaxed(ULONG_MAX - delta, base + TIMER_INI);
0062     writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
0063
0064     return 0;
0065 }
0066
0067 static int gx6605s_timer_shutdown(struct clock_event_device *ce)
0068 {
0069     void __iomem *base = timer_of_base(to_timer_of(ce));
0070
0071     writel_relaxed(0, base + TIMER_CONTRL);
0072     writel_relaxed(0, base + TIMER_CONFIG);
0073
0074     return 0;
0075 }
0076
0077 static struct timer_of to = {
0078     .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
0079     .clkevt = {
0080         .rating         = 300,
0081         .features       = CLOCK_EVT_FEAT_DYNIRQ |
0082                       CLOCK_EVT_FEAT_ONESHOT,
0083         .set_state_shutdown = gx6605s_timer_shutdown,
0084         .set_state_oneshot  = gx6605s_timer_set_oneshot,
0085         .set_next_event     = gx6605s_timer_set_next_event,
0086         .cpumask        = cpu_possible_mask,
0087     },
0088     .of_irq = {
0089         .handler        = gx6605s_timer_interrupt,
0090         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
0091     },
0092 };
0093
0094 static u64 notrace gx6605s_sched_clock_read(void)
0095 {
0096     void __iomem *base;
0097
0098     base = timer_of_base(&to) + CLKSRC_OFFSET;
0099
0100     return (u64)readl_relaxed(base + TIMER_VALUE);
0101 }
0102
0103 static void gx6605s_clkevt_init(void __iomem *base)
0104 {
0105     writel_relaxed(0, base + TIMER_DIV);
0106     writel_relaxed(0, base + TIMER_CONFIG);
0107
0108     clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), 2,
0109                     ULONG_MAX);
0110 }
0111
0112 static int gx6605s_clksrc_init(void __iomem *base)
0113 {
0114     writel_relaxed(0, base + TIMER_DIV);
0115     writel_relaxed(0, base + TIMER_INI);
0116
0117     writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
0118
0119     writel_relaxed(GX6605S_CONFIG_EN, base + TIMER_CONFIG);
0120
0121     writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
0122
0123     sched_clock_register(gx6605s_sched_clock_read, 32, timer_of_rate(&to));
0124
0125     return clocksource_mmio_init(base + TIMER_VALUE, "gx6605s",
0126             timer_of_rate(&to), 200, 32, clocksource_mmio_readl_up);
0127 }
0128
0129 static int __init gx6605s_timer_init(struct device_node *np)
0130 {
0131     int ret;
0132
0133     /*
0134      * The timer driver is for nationalchip gx6605s SOC and there are two
0135      * same timer in gx6605s. We use one for clkevt and another for clksrc.
0136      *
0137      * The timer is mmio map to access, so we need give mmio address in dts.
0138      *
0139      * It provides a 32bit countup timer and interrupt will be caused by
0140      * count-overflow.
0141      * So we need set-next-event by ULONG_MAX - delta in TIMER_INI reg.
0142      *
0143      * The counter at 0x0  offset is clock event.
0144      * The counter at 0x40 offset is clock source.
0145      * They are the same in hardware, just different used by driver.
0146      */
0147     ret = timer_of_init(np, &to);
0148     if (ret)
0149         return ret;
0150
0151     gx6605s_clkevt_init(timer_of_base(&to));
0152
0153     return gx6605s_clksrc_init(timer_of_base(&to) + CLKSRC_OFFSET);
0154 }
0155 TIMER_OF_DECLARE(csky_gx6605s_timer, "csky,gx6605s-timer", gx6605s_timer_init);