drivers/clocksource/timer-fttmr010.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Faraday Technology FTTMR010 timer driver
0004  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
0005  *
0006  * Based on a rewrite of arch/arm/mach-gemini/timer.c:
0007  * Copyright (C) 2001-2006 Storlink, Corp.
0008  * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
0009  */
0010 #include <linux/interrupt.h>
0011 #include <linux/io.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_irq.h>
0015 #include <linux/clockchips.h>
0016 #include <linux/clocksource.h>
0017 #include <linux/sched_clock.h>
0018 #include <linux/clk.h>
0019 #include <linux/slab.h>
0020 #include <linux/bitops.h>
0021 #include <linux/delay.h>
0022
0023 /*
0024  * Register definitions common for all the timer variants.
0025  */
0026 #define TIMER1_COUNT        (0x00)
0027 #define TIMER1_LOAD     (0x04)
0028 #define TIMER1_MATCH1       (0x08)
0029 #define TIMER1_MATCH2       (0x0c)
0030 #define TIMER2_COUNT        (0x10)
0031 #define TIMER2_LOAD     (0x14)
0032 #define TIMER2_MATCH1       (0x18)
0033 #define TIMER2_MATCH2       (0x1c)
0034 #define TIMER3_COUNT        (0x20)
0035 #define TIMER3_LOAD     (0x24)
0036 #define TIMER3_MATCH1       (0x28)
0037 #define TIMER3_MATCH2       (0x2c)
0038 #define TIMER_CR        (0x30)
0039
0040 /*
0041  * Control register set to clear for ast2600 only.
0042  */
0043 #define AST2600_TIMER_CR_CLR    (0x3c)
0044
0045 /*
0046  * Control register (TMC30) bit fields for fttmr010/gemini/moxart timers.
0047  */
0048 #define TIMER_1_CR_ENABLE   BIT(0)
0049 #define TIMER_1_CR_CLOCK    BIT(1)
0050 #define TIMER_1_CR_INT      BIT(2)
0051 #define TIMER_2_CR_ENABLE   BIT(3)
0052 #define TIMER_2_CR_CLOCK    BIT(4)
0053 #define TIMER_2_CR_INT      BIT(5)
0054 #define TIMER_3_CR_ENABLE   BIT(6)
0055 #define TIMER_3_CR_CLOCK    BIT(7)
0056 #define TIMER_3_CR_INT      BIT(8)
0057 #define TIMER_1_CR_UPDOWN   BIT(9)
0058 #define TIMER_2_CR_UPDOWN   BIT(10)
0059 #define TIMER_3_CR_UPDOWN   BIT(11)
0060
0061 /*
0062  * Control register (TMC30) bit fields for aspeed ast2400/ast2500 timers.
0063  * The aspeed timers move bits around in the control register and lacks
0064  * bits for setting the timer to count upwards.
0065  */
0066 #define TIMER_1_CR_ASPEED_ENABLE    BIT(0)
0067 #define TIMER_1_CR_ASPEED_CLOCK     BIT(1)
0068 #define TIMER_1_CR_ASPEED_INT       BIT(2)
0069 #define TIMER_2_CR_ASPEED_ENABLE    BIT(4)
0070 #define TIMER_2_CR_ASPEED_CLOCK     BIT(5)
0071 #define TIMER_2_CR_ASPEED_INT       BIT(6)
0072 #define TIMER_3_CR_ASPEED_ENABLE    BIT(8)
0073 #define TIMER_3_CR_ASPEED_CLOCK     BIT(9)
0074 #define TIMER_3_CR_ASPEED_INT       BIT(10)
0075
0076 /*
0077  * Interrupt status/mask register definitions for fttmr010/gemini/moxart
0078  * timers.
0079  * The registers don't exist and they are not needed on aspeed timers
0080  * because:
0081  *   - aspeed timer overflow interrupt is controlled by bits in Control
0082  *     Register (TMC30).
0083  *   - aspeed timers always generate interrupt when either one of the
0084  *     Match registers equals to Status register.
0085  */
0086 #define TIMER_INTR_STATE    (0x34)
0087 #define TIMER_INTR_MASK     (0x38)
0088 #define TIMER_1_INT_MATCH1  BIT(0)
0089 #define TIMER_1_INT_MATCH2  BIT(1)
0090 #define TIMER_1_INT_OVERFLOW    BIT(2)
0091 #define TIMER_2_INT_MATCH1  BIT(3)
0092 #define TIMER_2_INT_MATCH2  BIT(4)
0093 #define TIMER_2_INT_OVERFLOW    BIT(5)
0094 #define TIMER_3_INT_MATCH1  BIT(6)
0095 #define TIMER_3_INT_MATCH2  BIT(7)
0096 #define TIMER_3_INT_OVERFLOW    BIT(8)
0097 #define TIMER_INT_ALL_MASK  0x1ff
0098
0099 struct fttmr010 {
0100     void __iomem *base;
0101     unsigned int tick_rate;
0102     bool is_aspeed;
0103     u32 t1_enable_val;
0104     struct clock_event_device clkevt;
0105     int (*timer_shutdown)(struct clock_event_device *evt);
0106 #ifdef CONFIG_ARM
0107     struct delay_timer delay_timer;
0108 #endif
0109 };
0110
0111 /*
0112  * A local singleton used by sched_clock and delay timer reads, which are
0113  * fast and stateless
0114  */
0115 static struct fttmr010 *local_fttmr;
0116
0117 static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt)
0118 {
0119     return container_of(evt, struct fttmr010, clkevt);
0120 }
0121
0122 static unsigned long fttmr010_read_current_timer_up(void)
0123 {
0124     return readl(local_fttmr->base + TIMER2_COUNT);
0125 }
0126
0127 static unsigned long fttmr010_read_current_timer_down(void)
0128 {
0129     return ~readl(local_fttmr->base + TIMER2_COUNT);
0130 }
0131
0132 static u64 notrace fttmr010_read_sched_clock_up(void)
0133 {
0134     return fttmr010_read_current_timer_up();
0135 }
0136
0137 static u64 notrace fttmr010_read_sched_clock_down(void)
0138 {
0139     return fttmr010_read_current_timer_down();
0140 }
0141
0142 static int fttmr010_timer_set_next_event(unsigned long cycles,
0143                        struct clock_event_device *evt)
0144 {
0145     struct fttmr010 *fttmr010 = to_fttmr010(evt);
0146     u32 cr;
0147
0148     /* Stop */
0149     fttmr010->timer_shutdown(evt);
0150
0151     if (fttmr010->is_aspeed) {
0152         /*
0153          * ASPEED Timer Controller will load TIMER1_LOAD register
0154          * into TIMER1_COUNT register when the timer is re-enabled.
0155          */
0156         writel(cycles, fttmr010->base + TIMER1_LOAD);
0157     } else {
0158         /* Setup the match register forward in time */
0159         cr = readl(fttmr010->base + TIMER1_COUNT);
0160         writel(cr + cycles, fttmr010->base + TIMER1_MATCH1);
0161     }
0162
0163     /* Start */
0164     cr = readl(fttmr010->base + TIMER_CR);
0165     cr |= fttmr010->t1_enable_val;
0166     writel(cr, fttmr010->base + TIMER_CR);
0167
0168     return 0;
0169 }
0170
0171 static int ast2600_timer_shutdown(struct clock_event_device *evt)
0172 {
0173     struct fttmr010 *fttmr010 = to_fttmr010(evt);
0174
0175     /* Stop */
0176     writel(fttmr010->t1_enable_val, fttmr010->base + AST2600_TIMER_CR_CLR);
0177
0178     return 0;
0179 }
0180
0181 static int fttmr010_timer_shutdown(struct clock_event_device *evt)
0182 {
0183     struct fttmr010 *fttmr010 = to_fttmr010(evt);
0184     u32 cr;
0185
0186     /* Stop */
0187     cr = readl(fttmr010->base + TIMER_CR);
0188     cr &= ~fttmr010->t1_enable_val;
0189     writel(cr, fttmr010->base + TIMER_CR);
0190
0191     return 0;
0192 }
0193
0194 static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
0195 {
0196     struct fttmr010 *fttmr010 = to_fttmr010(evt);
0197     u32 cr;
0198
0199     /* Stop */
0200     fttmr010->timer_shutdown(evt);
0201
0202     /* Setup counter start from 0 or ~0 */
0203     writel(0, fttmr010->base + TIMER1_COUNT);
0204     if (fttmr010->is_aspeed) {
0205         writel(~0, fttmr010->base + TIMER1_LOAD);
0206     } else {
0207         writel(0, fttmr010->base + TIMER1_LOAD);
0208
0209         /* Enable interrupt */
0210         cr = readl(fttmr010->base + TIMER_INTR_MASK);
0211         cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
0212         cr |= TIMER_1_INT_MATCH1;
0213         writel(cr, fttmr010->base + TIMER_INTR_MASK);
0214     }
0215
0216     return 0;
0217 }
0218
0219 static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
0220 {
0221     struct fttmr010 *fttmr010 = to_fttmr010(evt);
0222     u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
0223     u32 cr;
0224
0225     /* Stop */
0226     fttmr010->timer_shutdown(evt);
0227
0228     /* Setup timer to fire at 1/HZ intervals. */
0229     if (fttmr010->is_aspeed) {
0230         writel(period, fttmr010->base + TIMER1_LOAD);
0231     } else {
0232         cr = 0xffffffff - (period - 1);
0233         writel(cr, fttmr010->base + TIMER1_COUNT);
0234         writel(cr, fttmr010->base + TIMER1_LOAD);
0235
0236         /* Enable interrupt on overflow */
0237         cr = readl(fttmr010->base + TIMER_INTR_MASK);
0238         cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
0239         cr |= TIMER_1_INT_OVERFLOW;
0240         writel(cr, fttmr010->base + TIMER_INTR_MASK);
0241     }
0242
0243     /* Start the timer */
0244     cr = readl(fttmr010->base + TIMER_CR);
0245     cr |= fttmr010->t1_enable_val;
0246     writel(cr, fttmr010->base + TIMER_CR);
0247
0248     return 0;
0249 }
0250
0251 /*
0252  * IRQ handler for the timer
0253  */
0254 static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
0255 {
0256     struct clock_event_device *evt = dev_id;
0257
0258     evt->event_handler(evt);
0259     return IRQ_HANDLED;
0260 }
0261
0262 static irqreturn_t ast2600_timer_interrupt(int irq, void *dev_id)
0263 {
0264     struct clock_event_device *evt = dev_id;
0265     struct fttmr010 *fttmr010 = to_fttmr010(evt);
0266
0267     writel(0x1, fttmr010->base + TIMER_INTR_STATE);
0268
0269     evt->event_handler(evt);
0270     return IRQ_HANDLED;
0271 }
0272
0273 static int __init fttmr010_common_init(struct device_node *np,
0274                        bool is_aspeed, bool is_ast2600)
0275 {
0276     struct fttmr010 *fttmr010;
0277     int irq;
0278     struct clk *clk;
0279     int ret;
0280     u32 val;
0281
0282     /*
0283      * These implementations require a clock reference.
0284      * FIXME: we currently only support clocking using PCLK
0285      * and using EXTCLK is not supported in the driver.
0286      */
0287     clk = of_clk_get_by_name(np, "PCLK");
0288     if (IS_ERR(clk)) {
0289         pr_err("could not get PCLK\n");
0290         return PTR_ERR(clk);
0291     }
0292     ret = clk_prepare_enable(clk);
0293     if (ret) {
0294         pr_err("failed to enable PCLK\n");
0295         return ret;
0296     }
0297
0298     fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
0299     if (!fttmr010) {
0300         ret = -ENOMEM;
0301         goto out_disable_clock;
0302     }
0303     fttmr010->tick_rate = clk_get_rate(clk);
0304
0305     fttmr010->base = of_iomap(np, 0);
0306     if (!fttmr010->base) {
0307         pr_err("Can't remap registers\n");
0308         ret = -ENXIO;
0309         goto out_free;
0310     }
0311     /* IRQ for timer 1 */
0312     irq = irq_of_parse_and_map(np, 0);
0313     if (irq <= 0) {
0314         pr_err("Can't parse IRQ\n");
0315         ret = -EINVAL;
0316         goto out_unmap;
0317     }
0318
0319     /*
0320      * The Aspeed timers move bits around in the control register.
0321      */
0322     if (is_aspeed) {
0323         fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE |
0324             TIMER_1_CR_ASPEED_INT;
0325         fttmr010->is_aspeed = true;
0326     } else {
0327         fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT;
0328
0329         /*
0330          * Reset the interrupt mask and status
0331          */
0332         writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
0333         writel(0, fttmr010->base + TIMER_INTR_STATE);
0334     }
0335
0336     /*
0337      * Enable timer 1 count up, timer 2 count up, except on Aspeed,
0338      * where everything just counts down.
0339      */
0340     if (is_aspeed)
0341         val = TIMER_2_CR_ASPEED_ENABLE;
0342     else {
0343         val = TIMER_2_CR_ENABLE | TIMER_1_CR_UPDOWN |
0344             TIMER_2_CR_UPDOWN;
0345     }
0346     writel(val, fttmr010->base + TIMER_CR);
0347
0348     /*
0349      * Setup free-running clocksource timer (interrupts
0350      * disabled.)
0351      */
0352     local_fttmr = fttmr010;
0353     writel(0, fttmr010->base + TIMER2_COUNT);
0354     writel(0, fttmr010->base + TIMER2_MATCH1);
0355     writel(0, fttmr010->base + TIMER2_MATCH2);
0356
0357     if (fttmr010->is_aspeed) {
0358         writel(~0, fttmr010->base + TIMER2_LOAD);
0359         clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
0360                       "FTTMR010-TIMER2",
0361                       fttmr010->tick_rate,
0362                       300, 32, clocksource_mmio_readl_down);
0363         sched_clock_register(fttmr010_read_sched_clock_down, 32,
0364                      fttmr010->tick_rate);
0365     } else {
0366         writel(0, fttmr010->base + TIMER2_LOAD);
0367         clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
0368                       "FTTMR010-TIMER2",
0369                       fttmr010->tick_rate,
0370                       300, 32, clocksource_mmio_readl_up);
0371         sched_clock_register(fttmr010_read_sched_clock_up, 32,
0372                      fttmr010->tick_rate);
0373     }
0374
0375     /*
0376      * Setup clockevent timer (interrupt-driven) on timer 1.
0377      */
0378     writel(0, fttmr010->base + TIMER1_COUNT);
0379     writel(0, fttmr010->base + TIMER1_LOAD);
0380     writel(0, fttmr010->base + TIMER1_MATCH1);
0381     writel(0, fttmr010->base + TIMER1_MATCH2);
0382
0383     if (is_ast2600) {
0384         fttmr010->timer_shutdown = ast2600_timer_shutdown;
0385         ret = request_irq(irq, ast2600_timer_interrupt,
0386                   IRQF_TIMER, "FTTMR010-TIMER1",
0387                   &fttmr010->clkevt);
0388     } else {
0389         fttmr010->timer_shutdown = fttmr010_timer_shutdown;
0390         ret = request_irq(irq, fttmr010_timer_interrupt,
0391                   IRQF_TIMER, "FTTMR010-TIMER1",
0392                   &fttmr010->clkevt);
0393     }
0394     if (ret) {
0395         pr_err("FTTMR010-TIMER1 no IRQ\n");
0396         goto out_unmap;
0397     }
0398
0399     fttmr010->clkevt.name = "FTTMR010-TIMER1";
0400     /* Reasonably fast and accurate clock event */
0401     fttmr010->clkevt.rating = 300;
0402     fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
0403         CLOCK_EVT_FEAT_ONESHOT;
0404     fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
0405     fttmr010->clkevt.set_state_shutdown = fttmr010->timer_shutdown;
0406     fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
0407     fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
0408     fttmr010->clkevt.tick_resume = fttmr010->timer_shutdown;
0409     fttmr010->clkevt.cpumask = cpumask_of(0);
0410     fttmr010->clkevt.irq = irq;
0411     clockevents_config_and_register(&fttmr010->clkevt,
0412                     fttmr010->tick_rate,
0413                     1, 0xffffffff);
0414
0415 #ifdef CONFIG_ARM
0416     /* Also use this timer for delays */
0417     if (fttmr010->is_aspeed)
0418         fttmr010->delay_timer.read_current_timer =
0419             fttmr010_read_current_timer_down;
0420     else
0421         fttmr010->delay_timer.read_current_timer =
0422             fttmr010_read_current_timer_up;
0423     fttmr010->delay_timer.freq = fttmr010->tick_rate;
0424     register_current_timer_delay(&fttmr010->delay_timer);
0425 #endif
0426
0427     return 0;
0428
0429 out_unmap:
0430     iounmap(fttmr010->base);
0431 out_free:
0432     kfree(fttmr010);
0433 out_disable_clock:
0434     clk_disable_unprepare(clk);
0435
0436     return ret;
0437 }
0438
0439 static __init int ast2600_timer_init(struct device_node *np)
0440 {
0441     return fttmr010_common_init(np, true, true);
0442 }
0443
0444 static __init int aspeed_timer_init(struct device_node *np)
0445 {
0446     return fttmr010_common_init(np, true, false);
0447 }
0448
0449 static __init int fttmr010_timer_init(struct device_node *np)
0450 {
0451     return fttmr010_common_init(np, false, false);
0452 }
0453
0454 TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
0455 TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
0456 TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
0457 TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
0458 TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);
0459 TIMER_OF_DECLARE(ast2600, "aspeed,ast2600-timer", ast2600_timer_init);