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0010 #define pr_fmt(fmt) "%s: " fmt, __func__
0011
0012 #include <linux/clk.h>
0013 #include <linux/clockchips.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/kernel.h>
0016 #include <linux/of_address.h>
0017 #include <linux/of_irq.h>
0018 #include <linux/sched_clock.h>
0019
0020 #include <clocksource/timer-davinci.h>
0021
0022 #define DAVINCI_TIMER_REG_TIM12 0x10
0023 #define DAVINCI_TIMER_REG_TIM34 0x14
0024 #define DAVINCI_TIMER_REG_PRD12 0x18
0025 #define DAVINCI_TIMER_REG_PRD34 0x1c
0026 #define DAVINCI_TIMER_REG_TCR 0x20
0027 #define DAVINCI_TIMER_REG_TGCR 0x24
0028
0029 #define DAVINCI_TIMER_TIMMODE_MASK GENMASK(3, 2)
0030 #define DAVINCI_TIMER_RESET_MASK GENMASK(1, 0)
0031 #define DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED BIT(2)
0032 #define DAVINCI_TIMER_UNRESET GENMASK(1, 0)
0033
0034 #define DAVINCI_TIMER_ENAMODE_MASK GENMASK(1, 0)
0035 #define DAVINCI_TIMER_ENAMODE_DISABLED 0x00
0036 #define DAVINCI_TIMER_ENAMODE_ONESHOT BIT(0)
0037 #define DAVINCI_TIMER_ENAMODE_PERIODIC BIT(1)
0038
0039 #define DAVINCI_TIMER_ENAMODE_SHIFT_TIM12 6
0040 #define DAVINCI_TIMER_ENAMODE_SHIFT_TIM34 22
0041
0042 #define DAVINCI_TIMER_MIN_DELTA 0x01
0043 #define DAVINCI_TIMER_MAX_DELTA 0xfffffffe
0044
0045 #define DAVINCI_TIMER_CLKSRC_BITS 32
0046
0047 #define DAVINCI_TIMER_TGCR_DEFAULT \
0048 (DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED | DAVINCI_TIMER_UNRESET)
0049
0050 struct davinci_clockevent {
0051 struct clock_event_device dev;
0052 void __iomem *base;
0053 unsigned int cmp_off;
0054 };
0055
0056
0057
0058
0059
0060 static struct {
0061 struct clocksource dev;
0062 void __iomem *base;
0063 unsigned int tim_off;
0064 } davinci_clocksource;
0065
0066 static struct davinci_clockevent *
0067 to_davinci_clockevent(struct clock_event_device *clockevent)
0068 {
0069 return container_of(clockevent, struct davinci_clockevent, dev);
0070 }
0071
0072 static unsigned int
0073 davinci_clockevent_read(struct davinci_clockevent *clockevent,
0074 unsigned int reg)
0075 {
0076 return readl_relaxed(clockevent->base + reg);
0077 }
0078
0079 static void davinci_clockevent_write(struct davinci_clockevent *clockevent,
0080 unsigned int reg, unsigned int val)
0081 {
0082 writel_relaxed(val, clockevent->base + reg);
0083 }
0084
0085 static void davinci_tim12_shutdown(void __iomem *base)
0086 {
0087 unsigned int tcr;
0088
0089 tcr = DAVINCI_TIMER_ENAMODE_DISABLED <<
0090 DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
0091
0092
0093
0094
0095
0096 tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC <<
0097 DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;
0098
0099 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
0100 }
0101
0102 static void davinci_tim12_set_oneshot(void __iomem *base)
0103 {
0104 unsigned int tcr;
0105
0106 tcr = DAVINCI_TIMER_ENAMODE_ONESHOT <<
0107 DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
0108
0109 tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC <<
0110 DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;
0111
0112 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
0113 }
0114
0115 static int davinci_clockevent_shutdown(struct clock_event_device *dev)
0116 {
0117 struct davinci_clockevent *clockevent;
0118
0119 clockevent = to_davinci_clockevent(dev);
0120
0121 davinci_tim12_shutdown(clockevent->base);
0122
0123 return 0;
0124 }
0125
0126 static int davinci_clockevent_set_oneshot(struct clock_event_device *dev)
0127 {
0128 struct davinci_clockevent *clockevent = to_davinci_clockevent(dev);
0129
0130 davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_TIM12, 0x0);
0131
0132 davinci_tim12_set_oneshot(clockevent->base);
0133
0134 return 0;
0135 }
0136
0137 static int
0138 davinci_clockevent_set_next_event_std(unsigned long cycles,
0139 struct clock_event_device *dev)
0140 {
0141 struct davinci_clockevent *clockevent = to_davinci_clockevent(dev);
0142
0143 davinci_clockevent_shutdown(dev);
0144
0145 davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_TIM12, 0x0);
0146 davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_PRD12, cycles);
0147
0148 davinci_clockevent_set_oneshot(dev);
0149
0150 return 0;
0151 }
0152
0153 static int
0154 davinci_clockevent_set_next_event_cmp(unsigned long cycles,
0155 struct clock_event_device *dev)
0156 {
0157 struct davinci_clockevent *clockevent = to_davinci_clockevent(dev);
0158 unsigned int curr_time;
0159
0160 curr_time = davinci_clockevent_read(clockevent,
0161 DAVINCI_TIMER_REG_TIM12);
0162 davinci_clockevent_write(clockevent,
0163 clockevent->cmp_off, curr_time + cycles);
0164
0165 return 0;
0166 }
0167
0168 static irqreturn_t davinci_timer_irq_timer(int irq, void *data)
0169 {
0170 struct davinci_clockevent *clockevent = data;
0171
0172 if (!clockevent_state_oneshot(&clockevent->dev))
0173 davinci_tim12_shutdown(clockevent->base);
0174
0175 clockevent->dev.event_handler(&clockevent->dev);
0176
0177 return IRQ_HANDLED;
0178 }
0179
0180 static u64 notrace davinci_timer_read_sched_clock(void)
0181 {
0182 return readl_relaxed(davinci_clocksource.base +
0183 davinci_clocksource.tim_off);
0184 }
0185
0186 static u64 davinci_clocksource_read(struct clocksource *dev)
0187 {
0188 return davinci_timer_read_sched_clock();
0189 }
0190
0191
0192
0193
0194
0195
0196 static void davinci_clocksource_init_tim34(void __iomem *base)
0197 {
0198 int tcr;
0199
0200 tcr = DAVINCI_TIMER_ENAMODE_PERIODIC <<
0201 DAVINCI_TIMER_ENAMODE_SHIFT_TIM34;
0202 tcr |= DAVINCI_TIMER_ENAMODE_ONESHOT <<
0203 DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
0204
0205 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34);
0206 writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD34);
0207 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
0208 }
0209
0210
0211
0212
0213
0214
0215 static void davinci_clocksource_init_tim12(void __iomem *base)
0216 {
0217 unsigned int tcr;
0218
0219 tcr = DAVINCI_TIMER_ENAMODE_PERIODIC <<
0220 DAVINCI_TIMER_ENAMODE_SHIFT_TIM12;
0221
0222 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12);
0223 writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD12);
0224 writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR);
0225 }
0226
0227 static void davinci_timer_init(void __iomem *base)
0228 {
0229
0230 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TCR);
0231
0232
0233
0234
0235 writel_relaxed(DAVINCI_TIMER_TGCR_DEFAULT,
0236 base + DAVINCI_TIMER_REG_TGCR);
0237
0238 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12);
0239 writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34);
0240 }
0241
0242 int __init davinci_timer_register(struct clk *clk,
0243 const struct davinci_timer_cfg *timer_cfg)
0244 {
0245 struct davinci_clockevent *clockevent;
0246 unsigned int tick_rate;
0247 void __iomem *base;
0248 int rv;
0249
0250 rv = clk_prepare_enable(clk);
0251 if (rv) {
0252 pr_err("Unable to prepare and enable the timer clock\n");
0253 return rv;
0254 }
0255
0256 if (!request_mem_region(timer_cfg->reg.start,
0257 resource_size(&timer_cfg->reg),
0258 "davinci-timer")) {
0259 pr_err("Unable to request memory region\n");
0260 return -EBUSY;
0261 }
0262
0263 base = ioremap(timer_cfg->reg.start, resource_size(&timer_cfg->reg));
0264 if (!base) {
0265 pr_err("Unable to map the register range\n");
0266 return -ENOMEM;
0267 }
0268
0269 davinci_timer_init(base);
0270 tick_rate = clk_get_rate(clk);
0271
0272 clockevent = kzalloc(sizeof(*clockevent), GFP_KERNEL);
0273 if (!clockevent)
0274 return -ENOMEM;
0275
0276 clockevent->dev.name = "tim12";
0277 clockevent->dev.features = CLOCK_EVT_FEAT_ONESHOT;
0278 clockevent->dev.cpumask = cpumask_of(0);
0279 clockevent->base = base;
0280
0281 if (timer_cfg->cmp_off) {
0282 clockevent->cmp_off = timer_cfg->cmp_off;
0283 clockevent->dev.set_next_event =
0284 davinci_clockevent_set_next_event_cmp;
0285 } else {
0286 clockevent->dev.set_next_event =
0287 davinci_clockevent_set_next_event_std;
0288 clockevent->dev.set_state_oneshot =
0289 davinci_clockevent_set_oneshot;
0290 clockevent->dev.set_state_shutdown =
0291 davinci_clockevent_shutdown;
0292 }
0293
0294 rv = request_irq(timer_cfg->irq[DAVINCI_TIMER_CLOCKEVENT_IRQ].start,
0295 davinci_timer_irq_timer, IRQF_TIMER,
0296 "clockevent/tim12", clockevent);
0297 if (rv) {
0298 pr_err("Unable to request the clockevent interrupt\n");
0299 return rv;
0300 }
0301
0302 davinci_clocksource.dev.rating = 300;
0303 davinci_clocksource.dev.read = davinci_clocksource_read;
0304 davinci_clocksource.dev.mask =
0305 CLOCKSOURCE_MASK(DAVINCI_TIMER_CLKSRC_BITS);
0306 davinci_clocksource.dev.flags = CLOCK_SOURCE_IS_CONTINUOUS;
0307 davinci_clocksource.base = base;
0308
0309 if (timer_cfg->cmp_off) {
0310 davinci_clocksource.dev.name = "tim12";
0311 davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM12;
0312 davinci_clocksource_init_tim12(base);
0313 } else {
0314 davinci_clocksource.dev.name = "tim34";
0315 davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM34;
0316 davinci_clocksource_init_tim34(base);
0317 }
0318
0319 clockevents_config_and_register(&clockevent->dev, tick_rate,
0320 DAVINCI_TIMER_MIN_DELTA,
0321 DAVINCI_TIMER_MAX_DELTA);
0322
0323 rv = clocksource_register_hz(&davinci_clocksource.dev, tick_rate);
0324 if (rv) {
0325 pr_err("Unable to register clocksource\n");
0326 return rv;
0327 }
0328
0329 sched_clock_register(davinci_timer_read_sched_clock,
0330 DAVINCI_TIMER_CLKSRC_BITS, tick_rate);
0331
0332 return 0;
0333 }
0334
0335 static int __init of_davinci_timer_register(struct device_node *np)
0336 {
0337 struct davinci_timer_cfg timer_cfg = { };
0338 struct clk *clk;
0339 int rv;
0340
0341 rv = of_address_to_resource(np, 0, &timer_cfg.reg);
0342 if (rv) {
0343 pr_err("Unable to get the register range for timer\n");
0344 return rv;
0345 }
0346
0347 rv = of_irq_to_resource_table(np, timer_cfg.irq,
0348 DAVINCI_TIMER_NUM_IRQS);
0349 if (rv != DAVINCI_TIMER_NUM_IRQS) {
0350 pr_err("Unable to get the interrupts for timer\n");
0351 return rv;
0352 }
0353
0354 clk = of_clk_get(np, 0);
0355 if (IS_ERR(clk)) {
0356 pr_err("Unable to get the timer clock\n");
0357 return PTR_ERR(clk);
0358 }
0359
0360 rv = davinci_timer_register(clk, &timer_cfg);
0361 if (rv)
0362 clk_put(clk);
0363
0364 return rv;
0365 }
0366 TIMER_OF_DECLARE(davinci_timer, "ti,da830-timer", of_davinci_timer_register);