drivers/clocksource/timer-cadence-ttc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * This file contains driver for the Cadence Triple Timer Counter Rev 06
0004  *
0005  *  Copyright (C) 2011-2013 Xilinx
0006  *
0007  * based on arch/mips/kernel/time.c timer driver
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/clockchips.h>
0013 #include <linux/clocksource.h>
0014 #include <linux/of_address.h>
0015 #include <linux/of_irq.h>
0016 #include <linux/slab.h>
0017 #include <linux/sched_clock.h>
0018 #include <linux/module.h>
0019 #include <linux/of_platform.h>
0020
0021 /*
0022  * This driver configures the 2 16/32-bit count-up timers as follows:
0023  *
0024  * T1: Timer 1, clocksource for generic timekeeping
0025  * T2: Timer 2, clockevent source for hrtimers
0026  * T3: Timer 3, <unused>
0027  *
0028  * The input frequency to the timer module for emulation is 2.5MHz which is
0029  * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
0030  * the timers are clocked at 78.125KHz (12.8 us resolution).
0031
0032  * The input frequency to the timer module in silicon is configurable and
0033  * obtained from device tree. The pre-scaler of 32 is used.
0034  */
0035
0036 /*
0037  * Timer Register Offset Definitions of Timer 1, Increment base address by 4
0038  * and use same offsets for Timer 2
0039  */
0040 #define TTC_CLK_CNTRL_OFFSET        0x00 /* Clock Control Reg, RW */
0041 #define TTC_CNT_CNTRL_OFFSET        0x0C /* Counter Control Reg, RW */
0042 #define TTC_COUNT_VAL_OFFSET        0x18 /* Counter Value Reg, RO */
0043 #define TTC_INTR_VAL_OFFSET     0x24 /* Interval Count Reg, RW */
0044 #define TTC_ISR_OFFSET      0x54 /* Interrupt Status Reg, RO */
0045 #define TTC_IER_OFFSET      0x60 /* Interrupt Enable Reg, RW */
0046
0047 #define TTC_CNT_CNTRL_DISABLE_MASK  0x1
0048
0049 #define TTC_CLK_CNTRL_CSRC_MASK     (1 << 5)    /* clock source */
0050 #define TTC_CLK_CNTRL_PSV_MASK      0x1e
0051 #define TTC_CLK_CNTRL_PSV_SHIFT     1
0052
0053 /*
0054  * Setup the timers to use pre-scaling, using a fixed value for now that will
0055  * work across most input frequency, but it may need to be more dynamic
0056  */
0057 #define PRESCALE_EXPONENT   11  /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
0058 #define PRESCALE        2048    /* The exponent must match this */
0059 #define CLK_CNTRL_PRESCALE  ((PRESCALE_EXPONENT - 1) << 1)
0060 #define CLK_CNTRL_PRESCALE_EN   1
0061 #define CNT_CNTRL_RESET     (1 << 4)
0062
0063 #define MAX_F_ERR 50
0064
0065 /**
0066  * struct ttc_timer - This definition defines local timer structure
0067  *
0068  * @base_addr:  Base address of timer
0069  * @freq:   Timer input clock frequency
0070  * @clk:    Associated clock source
0071  * @clk_rate_change_nb  Notifier block for clock rate changes
0072  */
0073 struct ttc_timer {
0074     void __iomem *base_addr;
0075     unsigned long freq;
0076     struct clk *clk;
0077     struct notifier_block clk_rate_change_nb;
0078 };
0079
0080 #define to_ttc_timer(x) \
0081         container_of(x, struct ttc_timer, clk_rate_change_nb)
0082
0083 struct ttc_timer_clocksource {
0084     u32         scale_clk_ctrl_reg_old;
0085     u32         scale_clk_ctrl_reg_new;
0086     struct ttc_timer    ttc;
0087     struct clocksource  cs;
0088 };
0089
0090 #define to_ttc_timer_clksrc(x) \
0091         container_of(x, struct ttc_timer_clocksource, cs)
0092
0093 struct ttc_timer_clockevent {
0094     struct ttc_timer        ttc;
0095     struct clock_event_device   ce;
0096 };
0097
0098 #define to_ttc_timer_clkevent(x) \
0099         container_of(x, struct ttc_timer_clockevent, ce)
0100
0101 static void __iomem *ttc_sched_clock_val_reg;
0102
0103 /**
0104  * ttc_set_interval - Set the timer interval value
0105  *
0106  * @timer:  Pointer to the timer instance
0107  * @cycles: Timer interval ticks
0108  **/
0109 static void ttc_set_interval(struct ttc_timer *timer,
0110                     unsigned long cycles)
0111 {
0112     u32 ctrl_reg;
0113
0114     /* Disable the counter, set the counter value  and re-enable counter */
0115     ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
0116     ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
0117     writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
0118
0119     writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
0120
0121     /*
0122      * Reset the counter (0x10) so that it starts from 0, one-shot
0123      * mode makes this needed for timing to be right.
0124      */
0125     ctrl_reg |= CNT_CNTRL_RESET;
0126     ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
0127     writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
0128 }
0129
0130 /**
0131  * ttc_clock_event_interrupt - Clock event timer interrupt handler
0132  *
0133  * @irq:    IRQ number of the Timer
0134  * @dev_id: void pointer to the ttc_timer instance
0135  *
0136  * returns: Always IRQ_HANDLED - success
0137  **/
0138 static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
0139 {
0140     struct ttc_timer_clockevent *ttce = dev_id;
0141     struct ttc_timer *timer = &ttce->ttc;
0142
0143     /* Acknowledge the interrupt and call event handler */
0144     readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
0145
0146     ttce->ce.event_handler(&ttce->ce);
0147
0148     return IRQ_HANDLED;
0149 }
0150
0151 /**
0152  * __ttc_clocksource_read - Reads the timer counter register
0153  *
0154  * returns: Current timer counter register value
0155  **/
0156 static u64 __ttc_clocksource_read(struct clocksource *cs)
0157 {
0158     struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
0159
0160     return (u64)readl_relaxed(timer->base_addr +
0161                 TTC_COUNT_VAL_OFFSET);
0162 }
0163
0164 static u64 notrace ttc_sched_clock_read(void)
0165 {
0166     return readl_relaxed(ttc_sched_clock_val_reg);
0167 }
0168
0169 /**
0170  * ttc_set_next_event - Sets the time interval for next event
0171  *
0172  * @cycles: Timer interval ticks
0173  * @evt:    Address of clock event instance
0174  *
0175  * returns: Always 0 - success
0176  **/
0177 static int ttc_set_next_event(unsigned long cycles,
0178                     struct clock_event_device *evt)
0179 {
0180     struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
0181     struct ttc_timer *timer = &ttce->ttc;
0182
0183     ttc_set_interval(timer, cycles);
0184     return 0;
0185 }
0186
0187 /**
0188  * ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer
0189  *
0190  * @evt:    Address of clock event instance
0191  **/
0192 static int ttc_shutdown(struct clock_event_device *evt)
0193 {
0194     struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
0195     struct ttc_timer *timer = &ttce->ttc;
0196     u32 ctrl_reg;
0197
0198     ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
0199     ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
0200     writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
0201     return 0;
0202 }
0203
0204 static int ttc_set_periodic(struct clock_event_device *evt)
0205 {
0206     struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
0207     struct ttc_timer *timer = &ttce->ttc;
0208
0209     ttc_set_interval(timer,
0210              DIV_ROUND_CLOSEST(ttce->ttc.freq, PRESCALE * HZ));
0211     return 0;
0212 }
0213
0214 static int ttc_resume(struct clock_event_device *evt)
0215 {
0216     struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
0217     struct ttc_timer *timer = &ttce->ttc;
0218     u32 ctrl_reg;
0219
0220     ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
0221     ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
0222     writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
0223     return 0;
0224 }
0225
0226 static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
0227         unsigned long event, void *data)
0228 {
0229     struct clk_notifier_data *ndata = data;
0230     struct ttc_timer *ttc = to_ttc_timer(nb);
0231     struct ttc_timer_clocksource *ttccs = container_of(ttc,
0232             struct ttc_timer_clocksource, ttc);
0233
0234     switch (event) {
0235     case PRE_RATE_CHANGE:
0236     {
0237         u32 psv;
0238         unsigned long factor, rate_low, rate_high;
0239
0240         if (ndata->new_rate > ndata->old_rate) {
0241             factor = DIV_ROUND_CLOSEST(ndata->new_rate,
0242                     ndata->old_rate);
0243             rate_low = ndata->old_rate;
0244             rate_high = ndata->new_rate;
0245         } else {
0246             factor = DIV_ROUND_CLOSEST(ndata->old_rate,
0247                     ndata->new_rate);
0248             rate_low = ndata->new_rate;
0249             rate_high = ndata->old_rate;
0250         }
0251
0252         if (!is_power_of_2(factor))
0253                 return NOTIFY_BAD;
0254
0255         if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
0256             return NOTIFY_BAD;
0257
0258         factor = __ilog2_u32(factor);
0259
0260         /*
0261          * store timer clock ctrl register so we can restore it in case
0262          * of an abort.
0263          */
0264         ttccs->scale_clk_ctrl_reg_old =
0265             readl_relaxed(ttccs->ttc.base_addr +
0266             TTC_CLK_CNTRL_OFFSET);
0267
0268         psv = (ttccs->scale_clk_ctrl_reg_old &
0269                 TTC_CLK_CNTRL_PSV_MASK) >>
0270                 TTC_CLK_CNTRL_PSV_SHIFT;
0271         if (ndata->new_rate < ndata->old_rate)
0272             psv -= factor;
0273         else
0274             psv += factor;
0275
0276         /* prescaler within legal range? */
0277         if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
0278             return NOTIFY_BAD;
0279
0280         ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
0281             ~TTC_CLK_CNTRL_PSV_MASK;
0282         ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;
0283
0284
0285         /* scale down: adjust divider in post-change notification */
0286         if (ndata->new_rate < ndata->old_rate)
0287             return NOTIFY_DONE;
0288
0289         /* scale up: adjust divider now - before frequency change */
0290         writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
0291                    ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
0292         break;
0293     }
0294     case POST_RATE_CHANGE:
0295         /* scale up: pre-change notification did the adjustment */
0296         if (ndata->new_rate > ndata->old_rate)
0297             return NOTIFY_OK;
0298
0299         /* scale down: adjust divider now - after frequency change */
0300         writel_relaxed(ttccs->scale_clk_ctrl_reg_new,
0301                    ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
0302         break;
0303
0304     case ABORT_RATE_CHANGE:
0305         /* we have to undo the adjustment in case we scale up */
0306         if (ndata->new_rate < ndata->old_rate)
0307             return NOTIFY_OK;
0308
0309         /* restore original register value */
0310         writel_relaxed(ttccs->scale_clk_ctrl_reg_old,
0311                    ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
0312         fallthrough;
0313     default:
0314         return NOTIFY_DONE;
0315     }
0316
0317     return NOTIFY_DONE;
0318 }
0319
0320 static int __init ttc_setup_clocksource(struct clk *clk, void __iomem *base,
0321                      u32 timer_width)
0322 {
0323     struct ttc_timer_clocksource *ttccs;
0324     int err;
0325
0326     ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
0327     if (!ttccs)
0328         return -ENOMEM;
0329
0330     ttccs->ttc.clk = clk;
0331
0332     err = clk_prepare_enable(ttccs->ttc.clk);
0333     if (err) {
0334         kfree(ttccs);
0335         return err;
0336     }
0337
0338     ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
0339
0340     ttccs->ttc.clk_rate_change_nb.notifier_call =
0341         ttc_rate_change_clocksource_cb;
0342     ttccs->ttc.clk_rate_change_nb.next = NULL;
0343
0344     err = clk_notifier_register(ttccs->ttc.clk,
0345                     &ttccs->ttc.clk_rate_change_nb);
0346     if (err)
0347         pr_warn("Unable to register clock notifier.\n");
0348
0349     ttccs->ttc.base_addr = base;
0350     ttccs->cs.name = "ttc_clocksource";
0351     ttccs->cs.rating = 200;
0352     ttccs->cs.read = __ttc_clocksource_read;
0353     ttccs->cs.mask = CLOCKSOURCE_MASK(timer_width);
0354     ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
0355
0356     /*
0357      * Setup the clock source counter to be an incrementing counter
0358      * with no interrupt and it rolls over at 0xFFFF. Pre-scale
0359      * it by 32 also. Let it start running now.
0360      */
0361     writel_relaxed(0x0,  ttccs->ttc.base_addr + TTC_IER_OFFSET);
0362     writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
0363              ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
0364     writel_relaxed(CNT_CNTRL_RESET,
0365              ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
0366
0367     err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
0368     if (err) {
0369         kfree(ttccs);
0370         return err;
0371     }
0372
0373     ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
0374     sched_clock_register(ttc_sched_clock_read, timer_width,
0375                  ttccs->ttc.freq / PRESCALE);
0376
0377     return 0;
0378 }
0379
0380 static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
0381         unsigned long event, void *data)
0382 {
0383     struct clk_notifier_data *ndata = data;
0384     struct ttc_timer *ttc = to_ttc_timer(nb);
0385     struct ttc_timer_clockevent *ttcce = container_of(ttc,
0386             struct ttc_timer_clockevent, ttc);
0387
0388     switch (event) {
0389     case POST_RATE_CHANGE:
0390         /* update cached frequency */
0391         ttc->freq = ndata->new_rate;
0392
0393         clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
0394
0395         fallthrough;
0396     case PRE_RATE_CHANGE:
0397     case ABORT_RATE_CHANGE:
0398     default:
0399         return NOTIFY_DONE;
0400     }
0401 }
0402
0403 static int __init ttc_setup_clockevent(struct clk *clk,
0404                        void __iomem *base, u32 irq)
0405 {
0406     struct ttc_timer_clockevent *ttcce;
0407     int err;
0408
0409     ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
0410     if (!ttcce)
0411         return -ENOMEM;
0412
0413     ttcce->ttc.clk = clk;
0414
0415     err = clk_prepare_enable(ttcce->ttc.clk);
0416     if (err)
0417         goto out_kfree;
0418
0419     ttcce->ttc.clk_rate_change_nb.notifier_call =
0420         ttc_rate_change_clockevent_cb;
0421     ttcce->ttc.clk_rate_change_nb.next = NULL;
0422
0423     err = clk_notifier_register(ttcce->ttc.clk,
0424                     &ttcce->ttc.clk_rate_change_nb);
0425     if (err) {
0426         pr_warn("Unable to register clock notifier.\n");
0427         goto out_kfree;
0428     }
0429
0430     ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
0431
0432     ttcce->ttc.base_addr = base;
0433     ttcce->ce.name = "ttc_clockevent";
0434     ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
0435     ttcce->ce.set_next_event = ttc_set_next_event;
0436     ttcce->ce.set_state_shutdown = ttc_shutdown;
0437     ttcce->ce.set_state_periodic = ttc_set_periodic;
0438     ttcce->ce.set_state_oneshot = ttc_shutdown;
0439     ttcce->ce.tick_resume = ttc_resume;
0440     ttcce->ce.rating = 200;
0441     ttcce->ce.irq = irq;
0442     ttcce->ce.cpumask = cpu_possible_mask;
0443
0444     /*
0445      * Setup the clock event timer to be an interval timer which
0446      * is prescaled by 32 using the interval interrupt. Leave it
0447      * disabled for now.
0448      */
0449     writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
0450     writel_relaxed(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
0451              ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
0452     writel_relaxed(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);
0453
0454     err = request_irq(irq, ttc_clock_event_interrupt,
0455               IRQF_TIMER, ttcce->ce.name, ttcce);
0456     if (err)
0457         goto out_kfree;
0458
0459     clockevents_config_and_register(&ttcce->ce,
0460             ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
0461
0462     return 0;
0463
0464 out_kfree:
0465     kfree(ttcce);
0466     return err;
0467 }
0468
0469 static int __init ttc_timer_probe(struct platform_device *pdev)
0470 {
0471     unsigned int irq;
0472     void __iomem *timer_baseaddr;
0473     struct clk *clk_cs, *clk_ce;
0474     static int initialized;
0475     int clksel, ret;
0476     u32 timer_width = 16;
0477     struct device_node *timer = pdev->dev.of_node;
0478
0479     if (initialized)
0480         return 0;
0481
0482     initialized = 1;
0483
0484     /*
0485      * Get the 1st Triple Timer Counter (TTC) block from the device tree
0486      * and use it. Note that the event timer uses the interrupt and it's the
0487      * 2nd TTC hence the irq_of_parse_and_map(,1)
0488      */
0489     timer_baseaddr = of_iomap(timer, 0);
0490     if (!timer_baseaddr) {
0491         pr_err("ERROR: invalid timer base address\n");
0492         return -ENXIO;
0493     }
0494
0495     irq = irq_of_parse_and_map(timer, 1);
0496     if (irq <= 0) {
0497         pr_err("ERROR: invalid interrupt number\n");
0498         return -EINVAL;
0499     }
0500
0501     of_property_read_u32(timer, "timer-width", &timer_width);
0502
0503     clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
0504     clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
0505     clk_cs = of_clk_get(timer, clksel);
0506     if (IS_ERR(clk_cs)) {
0507         pr_err("ERROR: timer input clock not found\n");
0508         return PTR_ERR(clk_cs);
0509     }
0510
0511     clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
0512     clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
0513     clk_ce = of_clk_get(timer, clksel);
0514     if (IS_ERR(clk_ce)) {
0515         pr_err("ERROR: timer input clock not found\n");
0516         return PTR_ERR(clk_ce);
0517     }
0518
0519     ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width);
0520     if (ret)
0521         return ret;
0522
0523     ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
0524     if (ret)
0525         return ret;
0526
0527     pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq);
0528
0529     return 0;
0530 }
0531
0532 static const struct of_device_id ttc_timer_of_match[] = {
0533     {.compatible = "cdns,ttc"},
0534     {},
0535 };
0536
0537 MODULE_DEVICE_TABLE(of, ttc_timer_of_match);
0538
0539 static struct platform_driver ttc_timer_driver = {
0540     .driver = {
0541         .name   = "cdns_ttc_timer",
0542         .of_match_table = ttc_timer_of_match,
0543     },
0544 };
0545 builtin_platform_driver_probe(ttc_timer_driver, ttc_timer_probe);