drivers/clocksource/timer-armada-370-xp.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Marvell Armada 370/XP SoC timer handling.
0004  *
0005  * Copyright (C) 2012 Marvell
0006  *
0007  * Lior Amsalem <alior@marvell.com>
0008  * Gregory CLEMENT <gregory.clement@free-electrons.com>
0009  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0010  *
0011  * Timer 0 is used as free-running clocksource, while timer 1 is
0012  * used as clock_event_device.
0013  *
0014  * ---
0015  * Clocksource driver for Armada 370 and Armada XP SoC.
0016  * This driver implements one compatible string for each SoC, given
0017  * each has its own characteristics:
0018  *
0019  *   * Armada 370 has no 25 MHz fixed timer.
0020  *
0021  *   * Armada XP cannot work properly without such 25 MHz fixed timer as
0022  *     doing otherwise leads to using a clocksource whose frequency varies
0023  *     when doing cpufreq frequency changes.
0024  *
0025  * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt
0026  */
0027
0028 #include <linux/init.h>
0029 #include <linux/platform_device.h>
0030 #include <linux/kernel.h>
0031 #include <linux/clk.h>
0032 #include <linux/cpu.h>
0033 #include <linux/timer.h>
0034 #include <linux/clockchips.h>
0035 #include <linux/interrupt.h>
0036 #include <linux/of.h>
0037 #include <linux/of_irq.h>
0038 #include <linux/of_address.h>
0039 #include <linux/irq.h>
0040 #include <linux/module.h>
0041 #include <linux/sched_clock.h>
0042 #include <linux/percpu.h>
0043 #include <linux/syscore_ops.h>
0044
0045 #include <asm/delay.h>
0046
0047 /*
0048  * Timer block registers.
0049  */
0050 #define TIMER_CTRL_OFF      0x0000
0051 #define  TIMER0_EN       BIT(0)
0052 #define  TIMER0_RELOAD_EN    BIT(1)
0053 #define  TIMER0_25MHZ            BIT(11)
0054 #define  TIMER0_DIV(div)         ((div) << 19)
0055 #define  TIMER1_EN       BIT(2)
0056 #define  TIMER1_RELOAD_EN    BIT(3)
0057 #define  TIMER1_25MHZ            BIT(12)
0058 #define  TIMER1_DIV(div)         ((div) << 22)
0059 #define TIMER_EVENTS_STATUS 0x0004
0060 #define  TIMER0_CLR_MASK         (~0x1)
0061 #define  TIMER1_CLR_MASK         (~0x100)
0062 #define TIMER0_RELOAD_OFF   0x0010
0063 #define TIMER0_VAL_OFF      0x0014
0064 #define TIMER1_RELOAD_OFF   0x0018
0065 #define TIMER1_VAL_OFF      0x001c
0066
0067 #define LCL_TIMER_EVENTS_STATUS 0x0028
0068 /* Global timers are connected to the coherency fabric clock, and the
0069    below divider reduces their incrementing frequency. */
0070 #define TIMER_DIVIDER_SHIFT     5
0071 #define TIMER_DIVIDER           (1 << TIMER_DIVIDER_SHIFT)
0072
0073 /*
0074  * SoC-specific data.
0075  */
0076 static void __iomem *timer_base, *local_base;
0077 static unsigned int timer_clk;
0078 static bool timer25Mhz = true;
0079 static u32 enable_mask;
0080
0081 /*
0082  * Number of timer ticks per jiffy.
0083  */
0084 static u32 ticks_per_jiffy;
0085
0086 static struct clock_event_device __percpu *armada_370_xp_evt;
0087
0088 static void local_timer_ctrl_clrset(u32 clr, u32 set)
0089 {
0090     writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
0091         local_base + TIMER_CTRL_OFF);
0092 }
0093
0094 static u64 notrace armada_370_xp_read_sched_clock(void)
0095 {
0096     return ~readl(timer_base + TIMER0_VAL_OFF);
0097 }
0098
0099 /*
0100  * Clockevent handling.
0101  */
0102 static int
0103 armada_370_xp_clkevt_next_event(unsigned long delta,
0104                 struct clock_event_device *dev)
0105 {
0106     /*
0107      * Clear clockevent timer interrupt.
0108      */
0109     writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
0110
0111     /*
0112      * Setup new clockevent timer value.
0113      */
0114     writel(delta, local_base + TIMER0_VAL_OFF);
0115
0116     /*
0117      * Enable the timer.
0118      */
0119     local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask);
0120     return 0;
0121 }
0122
0123 static int armada_370_xp_clkevt_shutdown(struct clock_event_device *evt)
0124 {
0125     /*
0126      * Disable timer.
0127      */
0128     local_timer_ctrl_clrset(TIMER0_EN, 0);
0129
0130     /*
0131      * ACK pending timer interrupt.
0132      */
0133     writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
0134     return 0;
0135 }
0136
0137 static int armada_370_xp_clkevt_set_periodic(struct clock_event_device *evt)
0138 {
0139     /*
0140      * Setup timer to fire at 1/HZ intervals.
0141      */
0142     writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF);
0143     writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF);
0144
0145     /*
0146      * Enable timer.
0147      */
0148     local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
0149     return 0;
0150 }
0151
0152 static int armada_370_xp_clkevt_irq;
0153
0154 static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id)
0155 {
0156     /*
0157      * ACK timer interrupt and call event handler.
0158      */
0159     struct clock_event_device *evt = dev_id;
0160
0161     writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS);
0162     evt->event_handler(evt);
0163
0164     return IRQ_HANDLED;
0165 }
0166
0167 /*
0168  * Setup the local clock events for a CPU.
0169  */
0170 static int armada_370_xp_timer_starting_cpu(unsigned int cpu)
0171 {
0172     struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu);
0173     u32 clr = 0, set = 0;
0174
0175     if (timer25Mhz)
0176         set = TIMER0_25MHZ;
0177     else
0178         clr = TIMER0_25MHZ;
0179     local_timer_ctrl_clrset(clr, set);
0180
0181     evt->name       = "armada_370_xp_per_cpu_tick";
0182     evt->features       = CLOCK_EVT_FEAT_ONESHOT |
0183                   CLOCK_EVT_FEAT_PERIODIC;
0184     evt->shift      = 32;
0185     evt->rating     = 300;
0186     evt->set_next_event = armada_370_xp_clkevt_next_event;
0187     evt->set_state_shutdown = armada_370_xp_clkevt_shutdown;
0188     evt->set_state_periodic = armada_370_xp_clkevt_set_periodic;
0189     evt->set_state_oneshot  = armada_370_xp_clkevt_shutdown;
0190     evt->tick_resume    = armada_370_xp_clkevt_shutdown;
0191     evt->irq        = armada_370_xp_clkevt_irq;
0192     evt->cpumask        = cpumask_of(cpu);
0193
0194     clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe);
0195     enable_percpu_irq(evt->irq, 0);
0196
0197     return 0;
0198 }
0199
0200 static int armada_370_xp_timer_dying_cpu(unsigned int cpu)
0201 {
0202     struct clock_event_device *evt = per_cpu_ptr(armada_370_xp_evt, cpu);
0203
0204     evt->set_state_shutdown(evt);
0205     disable_percpu_irq(evt->irq);
0206     return 0;
0207 }
0208
0209 static u32 timer0_ctrl_reg, timer0_local_ctrl_reg;
0210
0211 static int armada_370_xp_timer_suspend(void)
0212 {
0213     timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF);
0214     timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF);
0215     return 0;
0216 }
0217
0218 static void armada_370_xp_timer_resume(void)
0219 {
0220     writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
0221     writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
0222     writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF);
0223     writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF);
0224 }
0225
0226 static struct syscore_ops armada_370_xp_timer_syscore_ops = {
0227     .suspend    = armada_370_xp_timer_suspend,
0228     .resume     = armada_370_xp_timer_resume,
0229 };
0230
0231 static unsigned long armada_370_delay_timer_read(void)
0232 {
0233     return ~readl(timer_base + TIMER0_VAL_OFF);
0234 }
0235
0236 static struct delay_timer armada_370_delay_timer = {
0237     .read_current_timer = armada_370_delay_timer_read,
0238 };
0239
0240 static int __init armada_370_xp_timer_common_init(struct device_node *np)
0241 {
0242     u32 clr = 0, set = 0;
0243     int res;
0244
0245     timer_base = of_iomap(np, 0);
0246     if (!timer_base) {
0247         pr_err("Failed to iomap\n");
0248         return -ENXIO;
0249     }
0250
0251     local_base = of_iomap(np, 1);
0252     if (!local_base) {
0253         pr_err("Failed to iomap\n");
0254         return -ENXIO;
0255     }
0256
0257     if (timer25Mhz) {
0258         set = TIMER0_25MHZ;
0259         enable_mask = TIMER0_EN;
0260     } else {
0261         clr = TIMER0_25MHZ;
0262         enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
0263     }
0264     atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);
0265     local_timer_ctrl_clrset(clr, set);
0266
0267     /*
0268      * We use timer 0 as clocksource, and private(local) timer 0
0269      * for clockevents
0270      */
0271     armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);
0272
0273     ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
0274
0275     /*
0276      * Setup free-running clocksource timer (interrupts
0277      * disabled).
0278      */
0279     writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
0280     writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
0281
0282     atomic_io_modify(timer_base + TIMER_CTRL_OFF,
0283         TIMER0_RELOAD_EN | enable_mask,
0284         TIMER0_RELOAD_EN | enable_mask);
0285
0286     armada_370_delay_timer.freq = timer_clk;
0287     register_current_timer_delay(&armada_370_delay_timer);
0288
0289     /*
0290      * Set scale and timer for sched_clock.
0291      */
0292     sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk);
0293
0294     res = clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
0295                     "armada_370_xp_clocksource",
0296                     timer_clk, 300, 32, clocksource_mmio_readl_down);
0297     if (res) {
0298         pr_err("Failed to initialize clocksource mmio\n");
0299         return res;
0300     }
0301
0302     armada_370_xp_evt = alloc_percpu(struct clock_event_device);
0303     if (!armada_370_xp_evt)
0304         return -ENOMEM;
0305
0306     /*
0307      * Setup clockevent timer (interrupt-driven).
0308      */
0309     res = request_percpu_irq(armada_370_xp_clkevt_irq,
0310                 armada_370_xp_timer_interrupt,
0311                 "armada_370_xp_per_cpu_tick",
0312                 armada_370_xp_evt);
0313     /* Immediately configure the timer on the boot CPU */
0314     if (res) {
0315         pr_err("Failed to request percpu irq\n");
0316         return res;
0317     }
0318
0319     res = cpuhp_setup_state(CPUHP_AP_ARMADA_TIMER_STARTING,
0320                 "clockevents/armada:starting",
0321                 armada_370_xp_timer_starting_cpu,
0322                 armada_370_xp_timer_dying_cpu);
0323     if (res) {
0324         pr_err("Failed to setup hotplug state and timer\n");
0325         return res;
0326     }
0327
0328     register_syscore_ops(&armada_370_xp_timer_syscore_ops);
0329
0330     return 0;
0331 }
0332
0333 static int __init armada_xp_timer_init(struct device_node *np)
0334 {
0335     struct clk *clk = of_clk_get_by_name(np, "fixed");
0336     int ret;
0337
0338     if (IS_ERR(clk)) {
0339         pr_err("Failed to get clock\n");
0340         return PTR_ERR(clk);
0341     }
0342
0343     ret = clk_prepare_enable(clk);
0344     if (ret)
0345         return ret;
0346
0347     timer_clk = clk_get_rate(clk);
0348
0349     return armada_370_xp_timer_common_init(np);
0350 }
0351 TIMER_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
0352                armada_xp_timer_init);
0353
0354 static int __init armada_375_timer_init(struct device_node *np)
0355 {
0356     struct clk *clk;
0357     int ret;
0358
0359     clk = of_clk_get_by_name(np, "fixed");
0360     if (!IS_ERR(clk)) {
0361         ret = clk_prepare_enable(clk);
0362         if (ret)
0363             return ret;
0364         timer_clk = clk_get_rate(clk);
0365     } else {
0366
0367         /*
0368          * This fallback is required in order to retain proper
0369          * devicetree backwards compatibility.
0370          */
0371         clk = of_clk_get(np, 0);
0372
0373         /* Must have at least a clock */
0374         if (IS_ERR(clk)) {
0375             pr_err("Failed to get clock\n");
0376             return PTR_ERR(clk);
0377         }
0378
0379         ret = clk_prepare_enable(clk);
0380         if (ret)
0381             return ret;
0382
0383         timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
0384         timer25Mhz = false;
0385     }
0386
0387     return armada_370_xp_timer_common_init(np);
0388 }
0389 TIMER_OF_DECLARE(armada_375, "marvell,armada-375-timer",
0390                armada_375_timer_init);
0391
0392 static int __init armada_370_timer_init(struct device_node *np)
0393 {
0394     struct clk *clk;
0395     int ret;
0396
0397     clk = of_clk_get(np, 0);
0398     if (IS_ERR(clk)) {
0399         pr_err("Failed to get clock\n");
0400         return PTR_ERR(clk);
0401     }
0402
0403     ret = clk_prepare_enable(clk);
0404     if (ret)
0405         return ret;
0406
0407     timer_clk = clk_get_rate(clk) / TIMER_DIVIDER;
0408     timer25Mhz = false;
0409
0410     return armada_370_xp_timer_common_init(np);
0411 }
0412 TIMER_OF_DECLARE(armada_370, "marvell,armada-370-timer",
0413                armada_370_timer_init);