drivers/clocksource/samsung_pwm_timer.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
0004  *      http://www.samsung.com/
0005  *
0006  * samsung - Common hr-timer support (s3c and s5p)
0007  */
0008
0009 #include <linux/interrupt.h>
0010 #include <linux/irq.h>
0011 #include <linux/err.h>
0012 #include <linux/clk.h>
0013 #include <linux/clockchips.h>
0014 #include <linux/list.h>
0015 #include <linux/module.h>
0016 #include <linux/of.h>
0017 #include <linux/of_address.h>
0018 #include <linux/of_irq.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/slab.h>
0021 #include <linux/sched_clock.h>
0022
0023 #include <clocksource/samsung_pwm.h>
0024
0025 /*
0026  * Clocksource driver
0027  */
0028
0029 #define REG_TCFG0           0x00
0030 #define REG_TCFG1           0x04
0031 #define REG_TCON            0x08
0032 #define REG_TINT_CSTAT          0x44
0033
0034 #define REG_TCNTB(chan)         (0x0c + 12 * (chan))
0035 #define REG_TCMPB(chan)         (0x10 + 12 * (chan))
0036
0037 #define TCFG0_PRESCALER_MASK        0xff
0038 #define TCFG0_PRESCALER1_SHIFT      8
0039
0040 #define TCFG1_SHIFT(x)          ((x) * 4)
0041 #define TCFG1_MUX_MASK          0xf
0042
0043 /*
0044  * Each channel occupies 4 bits in TCON register, but there is a gap of 4
0045  * bits (one channel) after channel 0, so channels have different numbering
0046  * when accessing TCON register.
0047  *
0048  * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
0049  * in its set of bits is 2 as opposed to 3 for other channels.
0050  */
0051 #define TCON_START(chan)        (1 << (4 * (chan) + 0))
0052 #define TCON_MANUALUPDATE(chan)     (1 << (4 * (chan) + 1))
0053 #define TCON_INVERT(chan)       (1 << (4 * (chan) + 2))
0054 #define _TCON_AUTORELOAD(chan)      (1 << (4 * (chan) + 3))
0055 #define _TCON_AUTORELOAD4(chan)     (1 << (4 * (chan) + 2))
0056 #define TCON_AUTORELOAD(chan)       \
0057     ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
0058
0059 DEFINE_SPINLOCK(samsung_pwm_lock);
0060 EXPORT_SYMBOL(samsung_pwm_lock);
0061
0062 struct samsung_pwm_clocksource {
0063     void __iomem *base;
0064     const void __iomem *source_reg;
0065     unsigned int irq[SAMSUNG_PWM_NUM];
0066     struct samsung_pwm_variant variant;
0067
0068     struct clk *timerclk;
0069
0070     unsigned int event_id;
0071     unsigned int source_id;
0072     unsigned int tcnt_max;
0073     unsigned int tscaler_div;
0074     unsigned int tdiv;
0075
0076     unsigned long clock_count_per_tick;
0077 };
0078
0079 static struct samsung_pwm_clocksource pwm;
0080
0081 static void samsung_timer_set_prescale(unsigned int channel, u16 prescale)
0082 {
0083     unsigned long flags;
0084     u8 shift = 0;
0085     u32 reg;
0086
0087     if (channel >= 2)
0088         shift = TCFG0_PRESCALER1_SHIFT;
0089
0090     spin_lock_irqsave(&samsung_pwm_lock, flags);
0091
0092     reg = readl(pwm.base + REG_TCFG0);
0093     reg &= ~(TCFG0_PRESCALER_MASK << shift);
0094     reg |= (prescale - 1) << shift;
0095     writel(reg, pwm.base + REG_TCFG0);
0096
0097     spin_unlock_irqrestore(&samsung_pwm_lock, flags);
0098 }
0099
0100 static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)
0101 {
0102     u8 shift = TCFG1_SHIFT(channel);
0103     unsigned long flags;
0104     u32 reg;
0105     u8 bits;
0106
0107     bits = (fls(divisor) - 1) - pwm.variant.div_base;
0108
0109     spin_lock_irqsave(&samsung_pwm_lock, flags);
0110
0111     reg = readl(pwm.base + REG_TCFG1);
0112     reg &= ~(TCFG1_MUX_MASK << shift);
0113     reg |= bits << shift;
0114     writel(reg, pwm.base + REG_TCFG1);
0115
0116     spin_unlock_irqrestore(&samsung_pwm_lock, flags);
0117 }
0118
0119 static void samsung_time_stop(unsigned int channel)
0120 {
0121     unsigned long tcon;
0122     unsigned long flags;
0123
0124     if (channel > 0)
0125         ++channel;
0126
0127     spin_lock_irqsave(&samsung_pwm_lock, flags);
0128
0129     tcon = readl_relaxed(pwm.base + REG_TCON);
0130     tcon &= ~TCON_START(channel);
0131     writel_relaxed(tcon, pwm.base + REG_TCON);
0132
0133     spin_unlock_irqrestore(&samsung_pwm_lock, flags);
0134 }
0135
0136 static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
0137 {
0138     unsigned long tcon;
0139     unsigned long flags;
0140     unsigned int tcon_chan = channel;
0141
0142     if (tcon_chan > 0)
0143         ++tcon_chan;
0144
0145     spin_lock_irqsave(&samsung_pwm_lock, flags);
0146
0147     tcon = readl_relaxed(pwm.base + REG_TCON);
0148
0149     tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan));
0150     tcon |= TCON_MANUALUPDATE(tcon_chan);
0151
0152     writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel));
0153     writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));
0154     writel_relaxed(tcon, pwm.base + REG_TCON);
0155
0156     spin_unlock_irqrestore(&samsung_pwm_lock, flags);
0157 }
0158
0159 static void samsung_time_start(unsigned int channel, bool periodic)
0160 {
0161     unsigned long tcon;
0162     unsigned long flags;
0163
0164     if (channel > 0)
0165         ++channel;
0166
0167     spin_lock_irqsave(&samsung_pwm_lock, flags);
0168
0169     tcon = readl_relaxed(pwm.base + REG_TCON);
0170
0171     tcon &= ~TCON_MANUALUPDATE(channel);
0172     tcon |= TCON_START(channel);
0173
0174     if (periodic)
0175         tcon |= TCON_AUTORELOAD(channel);
0176     else
0177         tcon &= ~TCON_AUTORELOAD(channel);
0178
0179     writel_relaxed(tcon, pwm.base + REG_TCON);
0180
0181     spin_unlock_irqrestore(&samsung_pwm_lock, flags);
0182 }
0183
0184 static int samsung_set_next_event(unsigned long cycles,
0185                   struct clock_event_device *evt)
0186 {
0187     /*
0188      * This check is needed to account for internal rounding
0189      * errors inside clockevents core, which might result in
0190      * passing cycles = 0, which in turn would not generate any
0191      * timer interrupt and hang the system.
0192      *
0193      * Another solution would be to set up the clockevent device
0194      * with min_delta = 2, but this would unnecessarily increase
0195      * the minimum sleep period.
0196      */
0197     if (!cycles)
0198         cycles = 1;
0199
0200     samsung_time_setup(pwm.event_id, cycles);
0201     samsung_time_start(pwm.event_id, false);
0202
0203     return 0;
0204 }
0205
0206 static int samsung_shutdown(struct clock_event_device *evt)
0207 {
0208     samsung_time_stop(pwm.event_id);
0209     return 0;
0210 }
0211
0212 static int samsung_set_periodic(struct clock_event_device *evt)
0213 {
0214     samsung_time_stop(pwm.event_id);
0215     samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
0216     samsung_time_start(pwm.event_id, true);
0217     return 0;
0218 }
0219
0220 static void samsung_clockevent_resume(struct clock_event_device *cev)
0221 {
0222     samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
0223     samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
0224
0225     if (pwm.variant.has_tint_cstat) {
0226         u32 mask = (1 << pwm.event_id);
0227
0228         writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
0229     }
0230 }
0231
0232 static struct clock_event_device time_event_device = {
0233     .name           = "samsung_event_timer",
0234     .features       = CLOCK_EVT_FEAT_PERIODIC |
0235                   CLOCK_EVT_FEAT_ONESHOT,
0236     .rating         = 200,
0237     .set_next_event     = samsung_set_next_event,
0238     .set_state_shutdown = samsung_shutdown,
0239     .set_state_periodic = samsung_set_periodic,
0240     .set_state_oneshot  = samsung_shutdown,
0241     .tick_resume        = samsung_shutdown,
0242     .resume         = samsung_clockevent_resume,
0243 };
0244
0245 static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
0246 {
0247     struct clock_event_device *evt = dev_id;
0248
0249     if (pwm.variant.has_tint_cstat) {
0250         u32 mask = (1 << pwm.event_id);
0251
0252         writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
0253     }
0254
0255     evt->event_handler(evt);
0256
0257     return IRQ_HANDLED;
0258 }
0259
0260 static void __init samsung_clockevent_init(void)
0261 {
0262     unsigned long pclk;
0263     unsigned long clock_rate;
0264     unsigned int irq_number;
0265
0266     pclk = clk_get_rate(pwm.timerclk);
0267
0268     samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
0269     samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
0270
0271     clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
0272     pwm.clock_count_per_tick = clock_rate / HZ;
0273
0274     time_event_device.cpumask = cpumask_of(0);
0275     clockevents_config_and_register(&time_event_device,
0276                     clock_rate, 1, pwm.tcnt_max);
0277
0278     irq_number = pwm.irq[pwm.event_id];
0279     if (request_irq(irq_number, samsung_clock_event_isr,
0280             IRQF_TIMER | IRQF_IRQPOLL, "samsung_time_irq",
0281             &time_event_device))
0282         pr_err("%s: request_irq() failed\n", "samsung_time_irq");
0283
0284     if (pwm.variant.has_tint_cstat) {
0285         u32 mask = (1 << pwm.event_id);
0286
0287         writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
0288     }
0289 }
0290
0291 static void samsung_clocksource_suspend(struct clocksource *cs)
0292 {
0293     samsung_time_stop(pwm.source_id);
0294 }
0295
0296 static void samsung_clocksource_resume(struct clocksource *cs)
0297 {
0298     samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
0299     samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
0300
0301     samsung_time_setup(pwm.source_id, pwm.tcnt_max);
0302     samsung_time_start(pwm.source_id, true);
0303 }
0304
0305 static u64 notrace samsung_clocksource_read(struct clocksource *c)
0306 {
0307     return ~readl_relaxed(pwm.source_reg);
0308 }
0309
0310 static struct clocksource samsung_clocksource = {
0311     .name       = "samsung_clocksource_timer",
0312     .rating     = 250,
0313     .read       = samsung_clocksource_read,
0314     .suspend    = samsung_clocksource_suspend,
0315     .resume     = samsung_clocksource_resume,
0316     .flags      = CLOCK_SOURCE_IS_CONTINUOUS,
0317 };
0318
0319 /*
0320  * Override the global weak sched_clock symbol with this
0321  * local implementation which uses the clocksource to get some
0322  * better resolution when scheduling the kernel. We accept that
0323  * this wraps around for now, since it is just a relative time
0324  * stamp. (Inspired by U300 implementation.)
0325  */
0326 static u64 notrace samsung_read_sched_clock(void)
0327 {
0328     return samsung_clocksource_read(NULL);
0329 }
0330
0331 static int __init samsung_clocksource_init(void)
0332 {
0333     unsigned long pclk;
0334     unsigned long clock_rate;
0335
0336     pclk = clk_get_rate(pwm.timerclk);
0337
0338     samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
0339     samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
0340
0341     clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
0342
0343     samsung_time_setup(pwm.source_id, pwm.tcnt_max);
0344     samsung_time_start(pwm.source_id, true);
0345
0346     if (pwm.source_id == 4)
0347         pwm.source_reg = pwm.base + 0x40;
0348     else
0349         pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14;
0350
0351     sched_clock_register(samsung_read_sched_clock,
0352                  pwm.variant.bits, clock_rate);
0353
0354     samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
0355     return clocksource_register_hz(&samsung_clocksource, clock_rate);
0356 }
0357
0358 static void __init samsung_timer_resources(void)
0359 {
0360     clk_prepare_enable(pwm.timerclk);
0361
0362     pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
0363     if (pwm.variant.bits == 16) {
0364         pwm.tscaler_div = 25;
0365         pwm.tdiv = 2;
0366     } else {
0367         pwm.tscaler_div = 2;
0368         pwm.tdiv = 1;
0369     }
0370 }
0371
0372 /*
0373  * PWM master driver
0374  */
0375 static int __init _samsung_pwm_clocksource_init(void)
0376 {
0377     u8 mask;
0378     int channel;
0379
0380     mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
0381     channel = fls(mask) - 1;
0382     if (channel < 0) {
0383         pr_crit("failed to find PWM channel for clocksource\n");
0384         return -EINVAL;
0385     }
0386     pwm.source_id = channel;
0387
0388     mask &= ~(1 << channel);
0389     channel = fls(mask) - 1;
0390     if (channel < 0) {
0391         pr_crit("failed to find PWM channel for clock event\n");
0392         return -EINVAL;
0393     }
0394     pwm.event_id = channel;
0395
0396     samsung_timer_resources();
0397     samsung_clockevent_init();
0398
0399     return samsung_clocksource_init();
0400 }
0401
0402 void __init samsung_pwm_clocksource_init(void __iomem *base,
0403                      unsigned int *irqs,
0404                      const struct samsung_pwm_variant *variant)
0405 {
0406     pwm.base = base;
0407     memcpy(&pwm.variant, variant, sizeof(pwm.variant));
0408     memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));
0409
0410     pwm.timerclk = clk_get(NULL, "timers");
0411     if (IS_ERR(pwm.timerclk))
0412         panic("failed to get timers clock for timer");
0413
0414     _samsung_pwm_clocksource_init();
0415 }
0416
0417 #ifdef CONFIG_TIMER_OF
0418 static int __init samsung_pwm_alloc(struct device_node *np,
0419                     const struct samsung_pwm_variant *variant)
0420 {
0421     struct property *prop;
0422     const __be32 *cur;
0423     u32 val;
0424     int i, ret;
0425
0426     memcpy(&pwm.variant, variant, sizeof(pwm.variant));
0427     for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
0428         pwm.irq[i] = irq_of_parse_and_map(np, i);
0429
0430     of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
0431         if (val >= SAMSUNG_PWM_NUM) {
0432             pr_warn("%s: invalid channel index in samsung,pwm-outputs property\n", __func__);
0433             continue;
0434         }
0435         pwm.variant.output_mask |= 1 << val;
0436     }
0437
0438     pwm.base = of_iomap(np, 0);
0439     if (!pwm.base) {
0440         pr_err("%s: failed to map PWM registers\n", __func__);
0441         return -ENXIO;
0442     }
0443
0444     pwm.timerclk = of_clk_get_by_name(np, "timers");
0445     if (IS_ERR(pwm.timerclk)) {
0446         pr_crit("failed to get timers clock for timer\n");
0447         ret = PTR_ERR(pwm.timerclk);
0448         goto err_clk;
0449     }
0450
0451     ret = _samsung_pwm_clocksource_init();
0452     if (ret)
0453         goto err_clocksource;
0454
0455     return 0;
0456
0457 err_clocksource:
0458     clk_put(pwm.timerclk);
0459     pwm.timerclk = NULL;
0460 err_clk:
0461     iounmap(pwm.base);
0462     pwm.base = NULL;
0463
0464     return ret;
0465 }
0466
0467 static const struct samsung_pwm_variant s3c24xx_variant = {
0468     .bits       = 16,
0469     .div_base   = 1,
0470     .has_tint_cstat = false,
0471     .tclk_mask  = (1 << 4),
0472 };
0473
0474 static int __init s3c2410_pwm_clocksource_init(struct device_node *np)
0475 {
0476     return samsung_pwm_alloc(np, &s3c24xx_variant);
0477 }
0478 TIMER_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);
0479
0480 static const struct samsung_pwm_variant s3c64xx_variant = {
0481     .bits       = 32,
0482     .div_base   = 0,
0483     .has_tint_cstat = true,
0484     .tclk_mask  = (1 << 7) | (1 << 6) | (1 << 5),
0485 };
0486
0487 static int __init s3c64xx_pwm_clocksource_init(struct device_node *np)
0488 {
0489     return samsung_pwm_alloc(np, &s3c64xx_variant);
0490 }
0491 TIMER_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);
0492
0493 static const struct samsung_pwm_variant s5p64x0_variant = {
0494     .bits       = 32,
0495     .div_base   = 0,
0496     .has_tint_cstat = true,
0497     .tclk_mask  = 0,
0498 };
0499
0500 static int __init s5p64x0_pwm_clocksource_init(struct device_node *np)
0501 {
0502     return samsung_pwm_alloc(np, &s5p64x0_variant);
0503 }
0504 TIMER_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);
0505
0506 static const struct samsung_pwm_variant s5p_variant = {
0507     .bits       = 32,
0508     .div_base   = 0,
0509     .has_tint_cstat = true,
0510     .tclk_mask  = (1 << 5),
0511 };
0512
0513 static int __init s5p_pwm_clocksource_init(struct device_node *np)
0514 {
0515     return samsung_pwm_alloc(np, &s5p_variant);
0516 }
0517 TIMER_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
0518 #endif