drivers/clocksource/renesas-ostm.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas Timer Support - OSTM
0004  *
0005  * Copyright (C) 2017 Renesas Electronics America, Inc.
0006  * Copyright (C) 2017 Chris Brandt
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/clockchips.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/reset.h>
0014 #include <linux/sched_clock.h>
0015 #include <linux/slab.h>
0016
0017 #include "timer-of.h"
0018
0019 /*
0020  * The OSTM contains independent channels.
0021  * The first OSTM channel probed will be set up as a free running
0022  * clocksource. Additionally we will use this clocksource for the system
0023  * schedule timer sched_clock().
0024  *
0025  * The second (or more) channel probed will be set up as an interrupt
0026  * driven clock event.
0027  */
0028
0029 static void __iomem *system_clock;  /* For sched_clock() */
0030
0031 /* OSTM REGISTERS */
0032 #define OSTM_CMP        0x000   /* RW,32 */
0033 #define OSTM_CNT        0x004   /* R,32 */
0034 #define OSTM_TE         0x010   /* R,8 */
0035 #define OSTM_TS         0x014   /* W,8 */
0036 #define OSTM_TT         0x018   /* W,8 */
0037 #define OSTM_CTL        0x020   /* RW,8 */
0038
0039 #define TE          0x01
0040 #define TS          0x01
0041 #define TT          0x01
0042 #define CTL_PERIODIC        0x00
0043 #define CTL_ONESHOT     0x02
0044 #define CTL_FREERUN     0x02
0045
0046 static void ostm_timer_stop(struct timer_of *to)
0047 {
0048     if (readb(timer_of_base(to) + OSTM_TE) & TE) {
0049         writeb(TT, timer_of_base(to) + OSTM_TT);
0050
0051         /*
0052          * Read back the register simply to confirm the write operation
0053          * has completed since I/O writes can sometimes get queued by
0054          * the bus architecture.
0055          */
0056         while (readb(timer_of_base(to) + OSTM_TE) & TE)
0057             ;
0058     }
0059 }
0060
0061 static int __init ostm_init_clksrc(struct timer_of *to)
0062 {
0063     ostm_timer_stop(to);
0064
0065     writel(0, timer_of_base(to) + OSTM_CMP);
0066     writeb(CTL_FREERUN, timer_of_base(to) + OSTM_CTL);
0067     writeb(TS, timer_of_base(to) + OSTM_TS);
0068
0069     return clocksource_mmio_init(timer_of_base(to) + OSTM_CNT,
0070                      to->np->full_name, timer_of_rate(to), 300,
0071                      32, clocksource_mmio_readl_up);
0072 }
0073
0074 static u64 notrace ostm_read_sched_clock(void)
0075 {
0076     return readl(system_clock);
0077 }
0078
0079 static void __init ostm_init_sched_clock(struct timer_of *to)
0080 {
0081     system_clock = timer_of_base(to) + OSTM_CNT;
0082     sched_clock_register(ostm_read_sched_clock, 32, timer_of_rate(to));
0083 }
0084
0085 static int ostm_clock_event_next(unsigned long delta,
0086                  struct clock_event_device *ced)
0087 {
0088     struct timer_of *to = to_timer_of(ced);
0089
0090     ostm_timer_stop(to);
0091
0092     writel(delta, timer_of_base(to) + OSTM_CMP);
0093     writeb(CTL_ONESHOT, timer_of_base(to) + OSTM_CTL);
0094     writeb(TS, timer_of_base(to) + OSTM_TS);
0095
0096     return 0;
0097 }
0098
0099 static int ostm_shutdown(struct clock_event_device *ced)
0100 {
0101     struct timer_of *to = to_timer_of(ced);
0102
0103     ostm_timer_stop(to);
0104
0105     return 0;
0106 }
0107 static int ostm_set_periodic(struct clock_event_device *ced)
0108 {
0109     struct timer_of *to = to_timer_of(ced);
0110
0111     if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
0112         ostm_timer_stop(to);
0113
0114     writel(timer_of_period(to) - 1, timer_of_base(to) + OSTM_CMP);
0115     writeb(CTL_PERIODIC, timer_of_base(to) + OSTM_CTL);
0116     writeb(TS, timer_of_base(to) + OSTM_TS);
0117
0118     return 0;
0119 }
0120
0121 static int ostm_set_oneshot(struct clock_event_device *ced)
0122 {
0123     struct timer_of *to = to_timer_of(ced);
0124
0125     ostm_timer_stop(to);
0126
0127     return 0;
0128 }
0129
0130 static irqreturn_t ostm_timer_interrupt(int irq, void *dev_id)
0131 {
0132     struct clock_event_device *ced = dev_id;
0133
0134     if (clockevent_state_oneshot(ced))
0135         ostm_timer_stop(to_timer_of(ced));
0136
0137     /* notify clockevent layer */
0138     if (ced->event_handler)
0139         ced->event_handler(ced);
0140
0141     return IRQ_HANDLED;
0142 }
0143
0144 static int __init ostm_init_clkevt(struct timer_of *to)
0145 {
0146     struct clock_event_device *ced = &to->clkevt;
0147
0148     ced->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC;
0149     ced->set_state_shutdown = ostm_shutdown;
0150     ced->set_state_periodic = ostm_set_periodic;
0151     ced->set_state_oneshot = ostm_set_oneshot;
0152     ced->set_next_event = ostm_clock_event_next;
0153     ced->shift = 32;
0154     ced->rating = 300;
0155     ced->cpumask = cpumask_of(0);
0156     clockevents_config_and_register(ced, timer_of_rate(to), 0xf,
0157                     0xffffffff);
0158
0159     return 0;
0160 }
0161
0162 static int __init ostm_init(struct device_node *np)
0163 {
0164     struct reset_control *rstc;
0165     struct timer_of *to;
0166     int ret;
0167
0168     to = kzalloc(sizeof(*to), GFP_KERNEL);
0169     if (!to)
0170         return -ENOMEM;
0171
0172     rstc = of_reset_control_get_optional_exclusive(np, NULL);
0173     if (IS_ERR(rstc)) {
0174         ret = PTR_ERR(rstc);
0175         goto err_free;
0176     }
0177
0178     reset_control_deassert(rstc);
0179
0180     to->flags = TIMER_OF_BASE | TIMER_OF_CLOCK;
0181     if (system_clock) {
0182         /*
0183          * clock sources don't use interrupts, clock events do
0184          */
0185         to->flags |= TIMER_OF_IRQ;
0186         to->of_irq.flags = IRQF_TIMER | IRQF_IRQPOLL;
0187         to->of_irq.handler = ostm_timer_interrupt;
0188     }
0189
0190     ret = timer_of_init(np, to);
0191     if (ret)
0192         goto err_reset;
0193
0194     /*
0195      * First probed device will be used as system clocksource. Any
0196      * additional devices will be used as clock events.
0197      */
0198     if (!system_clock) {
0199         ret = ostm_init_clksrc(to);
0200         if (ret)
0201             goto err_cleanup;
0202
0203         ostm_init_sched_clock(to);
0204         pr_info("%pOF: used for clocksource\n", np);
0205     } else {
0206         ret = ostm_init_clkevt(to);
0207         if (ret)
0208             goto err_cleanup;
0209
0210         pr_info("%pOF: used for clock events\n", np);
0211     }
0212
0213     return 0;
0214
0215 err_cleanup:
0216     timer_of_cleanup(to);
0217 err_reset:
0218     reset_control_assert(rstc);
0219     reset_control_put(rstc);
0220 err_free:
0221     kfree(to);
0222     return ret;
0223 }
0224
0225 TIMER_OF_DECLARE(ostm, "renesas,ostm", ostm_init);
0226
0227 #ifdef CONFIG_ARCH_R9A07G044
0228 static int __init ostm_probe(struct platform_device *pdev)
0229 {
0230     struct device *dev = &pdev->dev;
0231
0232     return ostm_init(dev->of_node);
0233 }
0234
0235 static const struct of_device_id ostm_of_table[] = {
0236     { .compatible = "renesas,ostm", },
0237     { /* sentinel */ }
0238 };
0239
0240 static struct platform_driver ostm_device_driver = {
0241     .driver = {
0242         .name = "renesas_ostm",
0243         .of_match_table = of_match_ptr(ostm_of_table),
0244         .suppress_bind_attrs = true,
0245     },
0246 };
0247 builtin_platform_driver_probe(ostm_device_driver, ostm_probe);
0248 #endif