drivers/clocksource/nomadik-mtu.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2008 STMicroelectronics
0004  * Copyright (C) 2010 Alessandro Rubini
0005  * Copyright (C) 2010 Linus Walleij for ST-Ericsson
0006  */
0007 #include <linux/init.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/irq.h>
0010 #include <linux/io.h>
0011 #include <linux/clockchips.h>
0012 #include <linux/clocksource.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_irq.h>
0015 #include <linux/of_platform.h>
0016 #include <linux/clk.h>
0017 #include <linux/jiffies.h>
0018 #include <linux/delay.h>
0019 #include <linux/err.h>
0020 #include <linux/sched_clock.h>
0021 #include <asm/mach/time.h>
0022
0023 /*
0024  * The MTU device hosts four different counters, with 4 set of
0025  * registers. These are register names.
0026  */
0027
0028 #define MTU_IMSC    0x00    /* Interrupt mask set/clear */
0029 #define MTU_RIS     0x04    /* Raw interrupt status */
0030 #define MTU_MIS     0x08    /* Masked interrupt status */
0031 #define MTU_ICR     0x0C    /* Interrupt clear register */
0032
0033 /* per-timer registers take 0..3 as argument */
0034 #define MTU_LR(x)   (0x10 + 0x10 * (x) + 0x00)  /* Load value */
0035 #define MTU_VAL(x)  (0x10 + 0x10 * (x) + 0x04)  /* Current value */
0036 #define MTU_CR(x)   (0x10 + 0x10 * (x) + 0x08)  /* Control reg */
0037 #define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c)  /* At next overflow */
0038
0039 /* bits for the control register */
0040 #define MTU_CRn_ENA     0x80
0041 #define MTU_CRn_PERIODIC    0x40    /* if 0 = free-running */
0042 #define MTU_CRn_PRESCALE_MASK   0x0c
0043 #define MTU_CRn_PRESCALE_1      0x00
0044 #define MTU_CRn_PRESCALE_16     0x04
0045 #define MTU_CRn_PRESCALE_256        0x08
0046 #define MTU_CRn_32BITS      0x02
0047 #define MTU_CRn_ONESHOT     0x01    /* if 0 = wraps reloading from BGLR*/
0048
0049 /* Other registers are usual amba/primecell registers, currently not used */
0050 #define MTU_ITCR    0xff0
0051 #define MTU_ITOP    0xff4
0052
0053 #define MTU_PERIPH_ID0  0xfe0
0054 #define MTU_PERIPH_ID1  0xfe4
0055 #define MTU_PERIPH_ID2  0xfe8
0056 #define MTU_PERIPH_ID3  0xfeC
0057
0058 #define MTU_PCELL0  0xff0
0059 #define MTU_PCELL1  0xff4
0060 #define MTU_PCELL2  0xff8
0061 #define MTU_PCELL3  0xffC
0062
0063 static void __iomem *mtu_base;
0064 static bool clkevt_periodic;
0065 static u32 clk_prescale;
0066 static u32 nmdk_cycle;      /* write-once */
0067 static struct delay_timer mtu_delay_timer;
0068
0069 /*
0070  * Override the global weak sched_clock symbol with this
0071  * local implementation which uses the clocksource to get some
0072  * better resolution when scheduling the kernel.
0073  */
0074 static u64 notrace nomadik_read_sched_clock(void)
0075 {
0076     if (unlikely(!mtu_base))
0077         return 0;
0078
0079     return -readl(mtu_base + MTU_VAL(0));
0080 }
0081
0082 static unsigned long nmdk_timer_read_current_timer(void)
0083 {
0084     return ~readl_relaxed(mtu_base + MTU_VAL(0));
0085 }
0086
0087 /* Clockevent device: use one-shot mode */
0088 static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
0089 {
0090     writel(1 << 1, mtu_base + MTU_IMSC);
0091     writel(evt, mtu_base + MTU_LR(1));
0092     /* Load highest value, enable device, enable interrupts */
0093     writel(MTU_CRn_ONESHOT | clk_prescale |
0094            MTU_CRn_32BITS | MTU_CRn_ENA,
0095            mtu_base + MTU_CR(1));
0096
0097     return 0;
0098 }
0099
0100 static void nmdk_clkevt_reset(void)
0101 {
0102     if (clkevt_periodic) {
0103         /* Timer: configure load and background-load, and fire it up */
0104         writel(nmdk_cycle, mtu_base + MTU_LR(1));
0105         writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
0106
0107         writel(MTU_CRn_PERIODIC | clk_prescale |
0108                MTU_CRn_32BITS | MTU_CRn_ENA,
0109                mtu_base + MTU_CR(1));
0110         writel(1 << 1, mtu_base + MTU_IMSC);
0111     } else {
0112         /* Generate an interrupt to start the clockevent again */
0113         (void) nmdk_clkevt_next(nmdk_cycle, NULL);
0114     }
0115 }
0116
0117 static int nmdk_clkevt_shutdown(struct clock_event_device *evt)
0118 {
0119     writel(0, mtu_base + MTU_IMSC);
0120     /* disable timer */
0121     writel(0, mtu_base + MTU_CR(1));
0122     /* load some high default value */
0123     writel(0xffffffff, mtu_base + MTU_LR(1));
0124     return 0;
0125 }
0126
0127 static int nmdk_clkevt_set_oneshot(struct clock_event_device *evt)
0128 {
0129     clkevt_periodic = false;
0130     return 0;
0131 }
0132
0133 static int nmdk_clkevt_set_periodic(struct clock_event_device *evt)
0134 {
0135     clkevt_periodic = true;
0136     nmdk_clkevt_reset();
0137     return 0;
0138 }
0139
0140 static void nmdk_clksrc_reset(void)
0141 {
0142     /* Disable */
0143     writel(0, mtu_base + MTU_CR(0));
0144
0145     /* ClockSource: configure load and background-load, and fire it up */
0146     writel(nmdk_cycle, mtu_base + MTU_LR(0));
0147     writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
0148
0149     writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
0150            mtu_base + MTU_CR(0));
0151 }
0152
0153 static void nmdk_clkevt_resume(struct clock_event_device *cedev)
0154 {
0155     nmdk_clkevt_reset();
0156     nmdk_clksrc_reset();
0157 }
0158
0159 static struct clock_event_device nmdk_clkevt = {
0160     .name           = "mtu_1",
0161     .features       = CLOCK_EVT_FEAT_ONESHOT |
0162                   CLOCK_EVT_FEAT_PERIODIC |
0163                   CLOCK_EVT_FEAT_DYNIRQ,
0164     .rating         = 200,
0165     .set_state_shutdown = nmdk_clkevt_shutdown,
0166     .set_state_periodic = nmdk_clkevt_set_periodic,
0167     .set_state_oneshot  = nmdk_clkevt_set_oneshot,
0168     .set_next_event     = nmdk_clkevt_next,
0169     .resume         = nmdk_clkevt_resume,
0170 };
0171
0172 /*
0173  * IRQ Handler for timer 1 of the MTU block.
0174  */
0175 static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
0176 {
0177     struct clock_event_device *evdev = dev_id;
0178
0179     writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
0180     evdev->event_handler(evdev);
0181     return IRQ_HANDLED;
0182 }
0183
0184 static int __init nmdk_timer_init(void __iomem *base, int irq,
0185                    struct clk *pclk, struct clk *clk)
0186 {
0187     unsigned long rate;
0188     int ret;
0189     int min_ticks;
0190
0191     mtu_base = base;
0192
0193     BUG_ON(clk_prepare_enable(pclk));
0194     BUG_ON(clk_prepare_enable(clk));
0195
0196     /*
0197      * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
0198      * for ux500, and in one specific Ux500 case 32768 Hz.
0199      *
0200      * Use a divide-by-16 counter if the tick rate is more than 32MHz.
0201      * At 32 MHz, the timer (with 32 bit counter) can be programmed
0202      * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
0203      * with 16 gives too low timer resolution.
0204      */
0205     rate = clk_get_rate(clk);
0206     if (rate > 32000000) {
0207         rate /= 16;
0208         clk_prescale = MTU_CRn_PRESCALE_16;
0209     } else {
0210         clk_prescale = MTU_CRn_PRESCALE_1;
0211     }
0212
0213     /* Cycles for periodic mode */
0214     nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);
0215
0216
0217     /* Timer 0 is the free running clocksource */
0218     nmdk_clksrc_reset();
0219
0220     ret = clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
0221                     rate, 200, 32, clocksource_mmio_readl_down);
0222     if (ret) {
0223         pr_err("timer: failed to initialize clock source %s\n", "mtu_0");
0224         return ret;
0225     }
0226
0227     sched_clock_register(nomadik_read_sched_clock, 32, rate);
0228
0229     /* Timer 1 is used for events, register irq and clockevents */
0230     if (request_irq(irq, nmdk_timer_interrupt, IRQF_TIMER,
0231             "Nomadik Timer Tick", &nmdk_clkevt))
0232         pr_err("%s: request_irq() failed\n", "Nomadik Timer Tick");
0233     nmdk_clkevt.cpumask = cpumask_of(0);
0234     nmdk_clkevt.irq = irq;
0235     if (rate < 100000)
0236         min_ticks = 5;
0237     else
0238         min_ticks = 2;
0239     clockevents_config_and_register(&nmdk_clkevt, rate, min_ticks,
0240                     0xffffffffU);
0241
0242     mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer;
0243     mtu_delay_timer.freq = rate;
0244     register_current_timer_delay(&mtu_delay_timer);
0245
0246     return 0;
0247 }
0248
0249 static int __init nmdk_timer_of_init(struct device_node *node)
0250 {
0251     struct clk *pclk;
0252     struct clk *clk;
0253     void __iomem *base;
0254     int irq;
0255
0256     base = of_iomap(node, 0);
0257     if (!base) {
0258         pr_err("Can't remap registers\n");
0259         return -ENXIO;
0260     }
0261
0262     pclk = of_clk_get_by_name(node, "apb_pclk");
0263     if (IS_ERR(pclk)) {
0264         pr_err("could not get apb_pclk\n");
0265         return PTR_ERR(pclk);
0266     }
0267
0268     clk = of_clk_get_by_name(node, "timclk");
0269     if (IS_ERR(clk)) {
0270         pr_err("could not get timclk\n");
0271         return PTR_ERR(clk);
0272     }
0273
0274     irq = irq_of_parse_and_map(node, 0);
0275     if (irq <= 0) {
0276         pr_err("Can't parse IRQ\n");
0277         return -EINVAL;
0278     }
0279
0280     return nmdk_timer_init(base, irq, pclk, clk);
0281 }
0282 TIMER_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
0283                nmdk_timer_of_init);