drivers/clocksource/mxs_timer.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 //  Copyright (C) 2000-2001 Deep Blue Solutions
0004 //  Copyright (C) 2002 Shane Nay (shane@minirl.com)
0005 //  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
0006 //  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
0007 //  Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
0008
0009 #include <linux/err.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/irq.h>
0012 #include <linux/clockchips.h>
0013 #include <linux/clk.h>
0014 #include <linux/of.h>
0015 #include <linux/of_address.h>
0016 #include <linux/of_irq.h>
0017 #include <linux/stmp_device.h>
0018 #include <linux/sched_clock.h>
0019
0020 /*
0021  * There are 2 versions of the timrot on Freescale MXS-based SoCs.
0022  * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
0023  * extends the counter to 32 bits.
0024  *
0025  * The implementation uses two timers, one for clock_event and
0026  * another for clocksource. MX28 uses timrot 0 and 1, while MX23
0027  * uses 0 and 2.
0028  */
0029
0030 #define MX23_TIMROT_VERSION_OFFSET  0x0a0
0031 #define MX28_TIMROT_VERSION_OFFSET  0x120
0032 #define BP_TIMROT_MAJOR_VERSION     24
0033 #define BV_TIMROT_VERSION_1     0x01
0034 #define BV_TIMROT_VERSION_2     0x02
0035 #define timrot_is_v1()  (timrot_major_version == BV_TIMROT_VERSION_1)
0036
0037 /*
0038  * There are 4 registers for each timrotv2 instance, and 2 registers
0039  * for each timrotv1. So address step 0x40 in macros below strides
0040  * one instance of timrotv2 while two instances of timrotv1.
0041  *
0042  * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
0043  * on MX28 while timrot2 on MX23.
0044  */
0045 /* common between v1 and v2 */
0046 #define HW_TIMROT_ROTCTRL       0x00
0047 #define HW_TIMROT_TIMCTRLn(n)       (0x20 + (n) * 0x40)
0048 /* v1 only */
0049 #define HW_TIMROT_TIMCOUNTn(n)      (0x30 + (n) * 0x40)
0050 /* v2 only */
0051 #define HW_TIMROT_RUNNING_COUNTn(n) (0x30 + (n) * 0x40)
0052 #define HW_TIMROT_FIXED_COUNTn(n)   (0x40 + (n) * 0x40)
0053
0054 #define BM_TIMROT_TIMCTRLn_RELOAD   (1 << 6)
0055 #define BM_TIMROT_TIMCTRLn_UPDATE   (1 << 7)
0056 #define BM_TIMROT_TIMCTRLn_IRQ_EN   (1 << 14)
0057 #define BM_TIMROT_TIMCTRLn_IRQ      (1 << 15)
0058 #define BP_TIMROT_TIMCTRLn_SELECT   0
0059 #define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL     0x8
0060 #define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL     0xb
0061 #define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS    0xf
0062
0063 static struct clock_event_device mxs_clockevent_device;
0064
0065 static void __iomem *mxs_timrot_base;
0066 static u32 timrot_major_version;
0067
0068 static inline void timrot_irq_disable(void)
0069 {
0070     __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
0071              HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
0072 }
0073
0074 static inline void timrot_irq_enable(void)
0075 {
0076     __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
0077              HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET);
0078 }
0079
0080 static void timrot_irq_acknowledge(void)
0081 {
0082     __raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base +
0083              HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
0084 }
0085
0086 static u64 timrotv1_get_cycles(struct clocksource *cs)
0087 {
0088     return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
0089             & 0xffff0000) >> 16);
0090 }
0091
0092 static int timrotv1_set_next_event(unsigned long evt,
0093                     struct clock_event_device *dev)
0094 {
0095     /* timrot decrements the count */
0096     __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
0097
0098     return 0;
0099 }
0100
0101 static int timrotv2_set_next_event(unsigned long evt,
0102                     struct clock_event_device *dev)
0103 {
0104     /* timrot decrements the count */
0105     __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
0106
0107     return 0;
0108 }
0109
0110 static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
0111 {
0112     struct clock_event_device *evt = dev_id;
0113
0114     timrot_irq_acknowledge();
0115     evt->event_handler(evt);
0116
0117     return IRQ_HANDLED;
0118 }
0119
0120 static void mxs_irq_clear(char *state)
0121 {
0122     /* Disable interrupt in timer module */
0123     timrot_irq_disable();
0124
0125     /* Set event time into the furthest future */
0126     if (timrot_is_v1())
0127         __raw_writel(0xffff, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
0128     else
0129         __raw_writel(0xffffffff,
0130                  mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
0131
0132     /* Clear pending interrupt */
0133     timrot_irq_acknowledge();
0134     pr_debug("%s: changing mode to %s\n", __func__, state);
0135 }
0136
0137 static int mxs_shutdown(struct clock_event_device *evt)
0138 {
0139     mxs_irq_clear("shutdown");
0140
0141     return 0;
0142 }
0143
0144 static int mxs_set_oneshot(struct clock_event_device *evt)
0145 {
0146     if (clockevent_state_oneshot(evt))
0147         mxs_irq_clear("oneshot");
0148     timrot_irq_enable();
0149     return 0;
0150 }
0151
0152 static struct clock_event_device mxs_clockevent_device = {
0153     .name           = "mxs_timrot",
0154     .features       = CLOCK_EVT_FEAT_ONESHOT,
0155     .set_state_shutdown = mxs_shutdown,
0156     .set_state_oneshot  = mxs_set_oneshot,
0157     .tick_resume        = mxs_shutdown,
0158     .set_next_event     = timrotv2_set_next_event,
0159     .rating         = 200,
0160 };
0161
0162 static int __init mxs_clockevent_init(struct clk *timer_clk)
0163 {
0164     if (timrot_is_v1())
0165         mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
0166     mxs_clockevent_device.cpumask = cpumask_of(0);
0167     clockevents_config_and_register(&mxs_clockevent_device,
0168                     clk_get_rate(timer_clk),
0169                     timrot_is_v1() ? 0xf : 0x2,
0170                     timrot_is_v1() ? 0xfffe : 0xfffffffe);
0171
0172     return 0;
0173 }
0174
0175 static struct clocksource clocksource_mxs = {
0176     .name       = "mxs_timer",
0177     .rating     = 200,
0178     .read       = timrotv1_get_cycles,
0179     .mask       = CLOCKSOURCE_MASK(16),
0180     .flags      = CLOCK_SOURCE_IS_CONTINUOUS,
0181 };
0182
0183 static u64 notrace mxs_read_sched_clock_v2(void)
0184 {
0185     return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
0186 }
0187
0188 static int __init mxs_clocksource_init(struct clk *timer_clk)
0189 {
0190     unsigned int c = clk_get_rate(timer_clk);
0191
0192     if (timrot_is_v1())
0193         clocksource_register_hz(&clocksource_mxs, c);
0194     else {
0195         clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
0196             "mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
0197         sched_clock_register(mxs_read_sched_clock_v2, 32, c);
0198     }
0199
0200     return 0;
0201 }
0202
0203 static int __init mxs_timer_init(struct device_node *np)
0204 {
0205     struct clk *timer_clk;
0206     int irq, ret;
0207
0208     mxs_timrot_base = of_iomap(np, 0);
0209     WARN_ON(!mxs_timrot_base);
0210
0211     timer_clk = of_clk_get(np, 0);
0212     if (IS_ERR(timer_clk)) {
0213         pr_err("%s: failed to get clk\n", __func__);
0214         return PTR_ERR(timer_clk);
0215     }
0216
0217     ret = clk_prepare_enable(timer_clk);
0218     if (ret)
0219         return ret;
0220
0221     /*
0222      * Initialize timers to a known state
0223      */
0224     stmp_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
0225
0226     /* get timrot version */
0227     timrot_major_version = __raw_readl(mxs_timrot_base +
0228             (of_device_is_compatible(np, "fsl,imx23-timrot") ?
0229                         MX23_TIMROT_VERSION_OFFSET :
0230                         MX28_TIMROT_VERSION_OFFSET));
0231     timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
0232
0233     /* one for clock_event */
0234     __raw_writel((timrot_is_v1() ?
0235             BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
0236             BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
0237             BM_TIMROT_TIMCTRLn_UPDATE |
0238             BM_TIMROT_TIMCTRLn_IRQ_EN,
0239             mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
0240
0241     /* another for clocksource */
0242     __raw_writel((timrot_is_v1() ?
0243             BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
0244             BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
0245             BM_TIMROT_TIMCTRLn_RELOAD,
0246             mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
0247
0248     /* set clocksource timer fixed count to the maximum */
0249     if (timrot_is_v1())
0250         __raw_writel(0xffff,
0251             mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
0252     else
0253         __raw_writel(0xffffffff,
0254             mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
0255
0256     /* init and register the timer to the framework */
0257     ret = mxs_clocksource_init(timer_clk);
0258     if (ret)
0259         return ret;
0260
0261     ret = mxs_clockevent_init(timer_clk);
0262     if (ret)
0263         return ret;
0264
0265     /* Make irqs happen */
0266     irq = irq_of_parse_and_map(np, 0);
0267     if (irq <= 0)
0268         return -EINVAL;
0269
0270     return request_irq(irq, mxs_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
0271                "MXS Timer Tick", &mxs_clockevent_device);
0272 }
0273 TIMER_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init);